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wdenk858b1a62002-09-30 16:12:23 +00001/*
2 * (C) Copyright 2001
3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 *
24 * TODO: clean-up
25 */
26
27/*
28 * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
29 *
30 * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
31 * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
32 * parameters from the datasheet are:
33 * Tclk = 7.5ns (CL = 2)
34 * Trp = 15ns
35 * Trc = 60ns
36 * Trcd = 15ns
37 * Trfc = 66ns
38 *
39 * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
40 * period is 10ns and the parameters needed for the Timing Register are:
41 * CASL = CL = 2 clock cycles
42 * PTA = Trp = 15ns / 10ns = 2 clock cycles
43 * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
44 * LDF = 2 clock cycles (but can be extended to meet board-level timing)
45 * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
46 * RCD = Trcd = 15ns / 10ns= 2 clock cycles
47 *
48 * The actual bit settings in the register would be:
49 *
50 * CASL = 0b01
51 * PTA = 0b01
52 * CTP = 0b10
53 * LDF = 0b01
54 * RFTA = 0b011
55 * RCD = 0b01
56 *
57 * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
58 * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
59 * defined as Trc rather than Trfc.
60 * When using DIMM modules, most but not all of the required timing parameters can be read
61 * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
62 * are not available from the EEPROM
63 */
64
65#include <common.h>
66#include "mip405.h"
67#include <asm/processor.h>
68#include <405gp_i2c.h>
69#include <miiphy.h>
70#include "../common/common_util.h"
71#include <i2c.h>
wdenk27b207f2003-07-24 23:38:38 +000072#include <rtc.h>
wdenk858b1a62002-09-30 16:12:23 +000073extern block_dev_desc_t * scsi_get_dev(int dev);
74extern block_dev_desc_t * ide_get_dev(int dev);
75
76#undef SDRAM_DEBUG
wdenkf3e0de62003-06-04 15:05:30 +000077#define ENABLE_ECC /* for ecc boards */
wdenk858b1a62002-09-30 16:12:23 +000078#define FALSE 0
79#define TRUE 1
80
81/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
82#ifndef __ldiv_t_defined
83typedef struct {
84 long int quot; /* Quotient */
85 long int rem; /* Remainder */
86} ldiv_t;
87extern ldiv_t ldiv (long int __numer, long int __denom);
88# define __ldiv_t_defined 1
89#endif
90
91
92#define PLD_PART_REG PER_PLD_ADDR + 0
93#define PLD_VERS_REG PER_PLD_ADDR + 1
94#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
95#define PLD_IRQ_REG PER_PLD_ADDR + 3
96#define PLD_COM_MODE_REG PER_PLD_ADDR + 4
97#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
98
99#define MEGA_BYTE (1024*1024)
100
101typedef struct {
102 unsigned char boardtype; /* Board revision and Population Options */
103 unsigned char cal; /* cas Latency (will be programmend as cal-1) */
104 unsigned char trp; /* datain27 in clocks */
105 unsigned char trcd; /* datain29 in clocks */
106 unsigned char tras; /* datain30 in clocks */
107 unsigned char tctp; /* tras - trcd in clocks */
108 unsigned char am; /* Address Mod (will be programmed as am-1) */
109 unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
110 unsigned char ecc; /* if true, ecc is enabled */
111} sdram_t;
wdenkf3e0de62003-06-04 15:05:30 +0000112#if defined(CONFIG_MIP405T)
113const sdram_t sdram_table[] = {
wdenk27b207f2003-07-24 23:38:38 +0000114 { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
wdenkf3e0de62003-06-04 15:05:30 +0000115 3, /* Case Latenty = 3 */
116 3, /* trp 20ns / 7.5 ns datain[27] */
117 3, /* trcd 20ns /7.5 ns (datain[29]) */
118 6, /* tras 44ns /7.5 ns (datain[30]) */
119 4, /* tcpt 44 - 20ns = 24ns */
wdenk27b207f2003-07-24 23:38:38 +0000120 2, /* Address Mode = 2 (12x9x4) */
121 3, /* size value (32MByte) */
wdenkf3e0de62003-06-04 15:05:30 +0000122 0}, /* ECC disabled */
123 { 0xff, /* terminator */
124 0xff,
125 0xff,
126 0xff,
127 0xff,
128 0xff,
129 0xff,
130 0xff }
131};
132#else
wdenk858b1a62002-09-30 16:12:23 +0000133const sdram_t sdram_table[] = {
134 { 0x0f, /* Rev A, 128MByte -1 Board */
135 3, /* Case Latenty = 3 */
136 3, /* trp 20ns / 7.5 ns datain[27] */
wdenk33149b82003-05-23 11:38:58 +0000137 3, /* trcd 20ns /7.5 ns (datain[29]) */
138 6, /* tras 44ns /7.5 ns (datain[30]) */
wdenk858b1a62002-09-30 16:12:23 +0000139 4, /* tcpt 44 - 20ns = 24ns */
wdenk33149b82003-05-23 11:38:58 +0000140 3, /* Address Mode = 3 */
wdenk858b1a62002-09-30 16:12:23 +0000141 5, /* size value */
142 1}, /* ECC enabled */
143 { 0x07, /* Rev A, 64MByte -2 Board */
144 3, /* Case Latenty = 3 */
145 3, /* trp 20ns / 7.5 ns datain[27] */
wdenk33149b82003-05-23 11:38:58 +0000146 3, /* trcd 20ns /7.5 ns (datain[29]) */
147 6, /* tras 44ns /7.5 ns (datain[30]) */
wdenk858b1a62002-09-30 16:12:23 +0000148 4, /* tcpt 44 - 20ns = 24ns */
wdenk33149b82003-05-23 11:38:58 +0000149 2, /* Address Mode = 2 */
wdenk858b1a62002-09-30 16:12:23 +0000150 4, /* size value */
151 1}, /* ECC enabled */
wdenk3e386912003-04-05 00:53:31 +0000152 { 0x03, /* Rev A, 128MByte -4 Board */
153 3, /* Case Latenty = 3 */
154 3, /* trp 20ns / 7.5 ns datain[27] */
wdenk33149b82003-05-23 11:38:58 +0000155 3, /* trcd 20ns /7.5 ns (datain[29]) */
156 6, /* tras 44ns /7.5 ns (datain[30]) */
wdenk3e386912003-04-05 00:53:31 +0000157 4, /* tcpt 44 - 20ns = 24ns */
wdenk33149b82003-05-23 11:38:58 +0000158 3, /* Address Mode = 3 */
159 5, /* size value */
160 1}, /* ECC enabled */
161 { 0x1f, /* Rev B, 128MByte -3 Board */
162 3, /* Case Latenty = 3 */
163 3, /* trp 20ns / 7.5 ns datain[27] */
164 3, /* trcd 20ns /7.5 ns (datain[29]) */
165 6, /* tras 44ns /7.5 ns (datain[30]) */
166 4, /* tcpt 44 - 20ns = 24ns */
167 3, /* Address Mode = 3 */
wdenk3e386912003-04-05 00:53:31 +0000168 5, /* size value */
169 1}, /* ECC enabled */
wdenk858b1a62002-09-30 16:12:23 +0000170 { 0xff, /* terminator */
171 0xff,
172 0xff,
173 0xff,
174 0xff,
175 0xff,
176 0xff,
177 0xff }
178};
wdenkf3e0de62003-06-04 15:05:30 +0000179#endif /*CONFIG_MIP405T */
wdenk858b1a62002-09-30 16:12:23 +0000180void SDRAM_err (const char *s)
181{
182#ifndef SDRAM_DEBUG
183 DECLARE_GLOBAL_DATA_PTR;
184
185 (void) get_clocks ();
186 gd->baudrate = 9600;
187 serial_init ();
188#endif
189 serial_puts ("\n");
190 serial_puts (s);
191 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
192 for (;;);
193}
194
195
196unsigned char get_board_revcfg (void)
197{
198 out8 (PER_BOARD_ADDR, 0);
199 return (in8 (PER_BOARD_ADDR));
200}
201
202
203#ifdef SDRAM_DEBUG
204
205void write_hex (unsigned char i)
206{
207 char cc;
208
209 cc = i >> 4;
210 cc &= 0xf;
211 if (cc > 9)
212 serial_putc (cc + 55);
213 else
214 serial_putc (cc + 48);
215 cc = i & 0xf;
216 if (cc > 9)
217 serial_putc (cc + 55);
218 else
219 serial_putc (cc + 48);
220}
221
222void write_4hex (unsigned long val)
223{
224 write_hex ((unsigned char) (val >> 24));
225 write_hex ((unsigned char) (val >> 16));
226 write_hex ((unsigned char) (val >> 8));
227 write_hex ((unsigned char) val);
228}
229
230#endif
231
232
233int init_sdram (void)
234{
235 DECLARE_GLOBAL_DATA_PTR;
236
237 unsigned long tmp, baseaddr;
238 unsigned short i;
239 unsigned char trp_clocks,
240 trcd_clocks,
241 tras_clocks,
242 trc_clocks,
243 tctp_clocks;
244 unsigned char cal_val;
245 unsigned char bc;
wdenkf3e0de62003-06-04 15:05:30 +0000246 unsigned long sdram_tim, sdram_bank;
wdenk858b1a62002-09-30 16:12:23 +0000247
wdenkf3e0de62003-06-04 15:05:30 +0000248 /*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/
wdenk858b1a62002-09-30 16:12:23 +0000249 (void) get_clocks ();
250 gd->baudrate = 9600;
251 serial_init ();
wdenkf3e0de62003-06-04 15:05:30 +0000252 /* set up the pld */
253 mtdcr (ebccfga, pb7ap);
254 mtdcr (ebccfgd, PLD_AP);
255 mtdcr (ebccfga, pb7cr);
256 mtdcr (ebccfgd, PLD_CR);
257 /* THIS IS OBSOLETE */
258 /* set up the board rev reg*/
259 mtdcr (ebccfga, pb5ap);
260 mtdcr (ebccfgd, BOARD_AP);
261 mtdcr (ebccfga, pb5cr);
262 mtdcr (ebccfgd, BOARD_CR);
263#ifdef SDRAM_DEBUG
264 /* get all informations from PLD */
265 serial_puts ("\nPLD Part 0x");
266 bc = in8 (PLD_PART_REG);
267 write_hex (bc);
268 serial_puts ("\nPLD Vers 0x");
269 bc = in8 (PLD_VERS_REG);
270 write_hex (bc);
271 serial_puts ("\nBoard Rev 0x");
272 bc = in8 (PLD_BOARD_CFG_REG);
273 write_hex (bc);
274 serial_puts ("\n");
275#endif
276 /* check board */
277 bc = in8 (PLD_PART_REG);
278#if defined(CONFIG_MIP405T)
279 if((bc & 0x80)==0)
280 SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
281#else
282 if((bc & 0x80)==0x80)
283 SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
284#endif
wdenkf3e0de62003-06-04 15:05:30 +0000285 /* set-up the chipselect machine */
wdenk858b1a62002-09-30 16:12:23 +0000286 mtdcr (ebccfga, pb0cr); /* get cs0 config reg */
wdenkf3e0de62003-06-04 15:05:30 +0000287 tmp = mfdcr (ebccfgd);
288 if ((tmp & 0x00002000) == 0) {
wdenk858b1a62002-09-30 16:12:23 +0000289 /* MPS Boot, set up the flash */
290 mtdcr (ebccfga, pb1ap);
291 mtdcr (ebccfgd, FLASH_AP);
292 mtdcr (ebccfga, pb1cr);
293 mtdcr (ebccfgd, FLASH_CR);
294 } else {
295 /* Flash boot, set up the MPS */
296 mtdcr (ebccfga, pb1ap);
297 mtdcr (ebccfgd, MPS_AP);
298 mtdcr (ebccfga, pb1cr);
299 mtdcr (ebccfgd, MPS_CR);
300 }
301 /* set up UART0 (CS2) and UART1 (CS3) */
302 mtdcr (ebccfga, pb2ap);
303 mtdcr (ebccfgd, UART0_AP);
304 mtdcr (ebccfga, pb2cr);
305 mtdcr (ebccfgd, UART0_CR);
306 mtdcr (ebccfga, pb3ap);
307 mtdcr (ebccfgd, UART1_AP);
308 mtdcr (ebccfga, pb3cr);
309 mtdcr (ebccfgd, UART1_CR);
wdenkf3e0de62003-06-04 15:05:30 +0000310 bc = in8 (PLD_BOARD_CFG_REG);
wdenk858b1a62002-09-30 16:12:23 +0000311#ifdef SDRAM_DEBUG
312 serial_puts ("\nstart SDRAM Setup\n");
313 serial_puts ("\nBoard Rev: ");
314 write_hex (bc);
315 serial_puts ("\n");
316#endif
317 i = 0;
318 baseaddr = CFG_SDRAM_BASE;
319 while (sdram_table[i].sz != 0xff) {
320 if (sdram_table[i].boardtype == bc)
321 break;
322 i++;
323 }
324 if (sdram_table[i].boardtype != bc)
325 SDRAM_err ("No SDRAM table found for this board!!!\n");
326#ifdef SDRAM_DEBUG
327 serial_puts (" found table ");
328 write_hex (i);
329 serial_puts (" \n");
330#endif
wdenk27b207f2003-07-24 23:38:38 +0000331 /* since the ECC initialisation needs some time,
332 * we show that we're alive
333 */
334 if (sdram_table[i].ecc)
335 serial_puts ("\nInitializing SDRAM, Please stand by");
wdenk858b1a62002-09-30 16:12:23 +0000336 cal_val = sdram_table[i].cal - 1; /* Cas Latency */
337 trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
338 trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
339 tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
340 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
341 tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */
342 /* trc_clocks is sum of trp_clocks + tras_clocks */
343 trc_clocks = trp_clocks + tras_clocks;
344 /* get SDRAM timing register */
345 mtdcr (memcfga, mem_sdtr1);
346 sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;
347 /* insert CASL value */
348 sdram_tim |= ((unsigned long) (cal_val)) << 23;
349 /* insert PTA value */
350 sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
351 /* insert CTP value */
352 sdram_tim |=
353 ((unsigned long) (trc_clocks - trp_clocks -
354 trcd_clocks)) << 16;
355 /* insert LDF (always 01) */
356 sdram_tim |= ((unsigned long) 0x01) << 14;
357 /* insert RFTA value */
358 sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
359 /* insert RCD value */
360 sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
361
362 tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
363 /* insert SZ value; */
364 tmp |= ((unsigned long) sdram_table[i].sz << 17);
365 /* get SDRAM bank 0 register */
366 mtdcr (memcfga, mem_mb0cf);
367 sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;
368 sdram_bank |= (baseaddr | tmp | 0x01);
369
370#ifdef SDRAM_DEBUG
371 serial_puts ("sdtr: ");
372 write_4hex (sdram_tim);
373 serial_puts ("\n");
374#endif
375
376 /* write SDRAM timing register */
377 mtdcr (memcfga, mem_sdtr1);
378 mtdcr (memcfgd, sdram_tim);
379
380#ifdef SDRAM_DEBUG
381 serial_puts ("mb0cf: ");
382 write_4hex (sdram_bank);
383 serial_puts ("\n");
384#endif
385
386 /* write SDRAM bank 0 register */
387 mtdcr (memcfga, mem_mb0cf);
388 mtdcr (memcfgd, sdram_bank);
389
390 if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
391 /* get SDRAM refresh interval register */
392 mtdcr (memcfga, mem_rtr);
393 tmp = mfdcr (memcfgd) & ~0x3FF80000;
394 tmp |= 0x07F00000;
395 } else {
396 /* get SDRAM refresh interval register */
397 mtdcr (memcfga, mem_rtr);
398 tmp = mfdcr (memcfgd) & ~0x3FF80000;
399 tmp |= 0x05F00000;
400 }
401 /* write SDRAM refresh interval register */
402 mtdcr (memcfga, mem_rtr);
403 mtdcr (memcfgd, tmp);
404 /* enable ECC if used */
wdenkf3e0de62003-06-04 15:05:30 +0000405#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
wdenk858b1a62002-09-30 16:12:23 +0000406 if (sdram_table[i].ecc) {
407 /* disable checking for all banks */
wdenkf3e0de62003-06-04 15:05:30 +0000408 unsigned long *p;
wdenk858b1a62002-09-30 16:12:23 +0000409#ifdef SDRAM_DEBUG
410 serial_puts ("disable ECC.. ");
411#endif
412 mtdcr (memcfga, mem_ecccf);
413 tmp = mfdcr (memcfgd);
414 tmp &= 0xff0fffff; /* disable all banks */
415 mtdcr (memcfga, mem_ecccf);
416 /* set up SDRAM Controller with ECC enabled */
417#ifdef SDRAM_DEBUG
418 serial_puts ("setup SDRAM Controller.. ");
419#endif
420 mtdcr (memcfgd, tmp);
421 mtdcr (memcfga, mem_mcopt1);
422 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
423 mtdcr (memcfga, mem_mcopt1);
424 mtdcr (memcfgd, tmp);
425 udelay (600);
426#ifdef SDRAM_DEBUG
427 serial_puts ("fill the memory..\n");
428#endif
429 serial_puts (".");
430 /* now, fill all the memory */
431 tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
432 p = (unsigned long) 0;
433 while ((unsigned long) p < tmp) {
434 *p++ = 0L;
435 if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
436 serial_puts (".");
wdenk858b1a62002-09-30 16:12:23 +0000437 }
438 /* enable bank 0 */
439 serial_puts (".");
440#ifdef SDRAM_DEBUG
441 serial_puts ("enable ECC\n");
442#endif
443 udelay (400);
444 mtdcr (memcfga, mem_ecccf);
445 tmp = mfdcr (memcfgd);
446 tmp |= 0x00800000; /* enable bank 0 */
447 mtdcr (memcfgd, tmp);
448 udelay (400);
449 } else
450#endif
451 {
452 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
453 mtdcr (memcfga, mem_mcopt1);
454 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
455 mtdcr (memcfga, mem_mcopt1);
456 mtdcr (memcfgd, tmp);
457 udelay (400);
458 }
459 serial_puts ("\n");
460 return (0);
461}
462
463int board_pre_init (void)
464{
465 init_sdram ();
466
467 /*-------------------------------------------------------------------------+
468 | Interrupt controller setup for the PIP405 board.
469 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
470 | IRQ 16 405GP internally generated; active low; level sensitive
471 | IRQ 17-24 RESERVED
472 | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
473 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
474 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
475 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
476 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
477 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
478 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
479 | Note for MIP405 board:
480 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
481 | the Interrupt Controller in the South Bridge has caused the
482 | interrupt. The IC must be read to determine which device
483 | caused the interrupt.
484 |
485 +-------------------------------------------------------------------------*/
486 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
487 mtdcr (uicer, 0x00000000); /* disable all ints */
488 mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
489 mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
490 mtdcr (uictr, 0x10000000); /* set int trigger levels */
491 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
492 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
493 return 0;
494}
495
496
497/*
498 * Get some PLD Registers
499 */
500
501unsigned short get_pld_parvers (void)
502{
503 unsigned short result;
504 unsigned char rc;
505
506 rc = in8 (PLD_PART_REG);
507 result = (unsigned short) rc << 8;
508 rc = in8 (PLD_VERS_REG);
509 result |= rc;
510 return result;
511}
512
513
wdenk858b1a62002-09-30 16:12:23 +0000514void user_led0 (unsigned char on)
515{
516 if (on)
517 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
518 else
519 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
520}
521
522
523void ide_set_reset (int idereset)
524{
525 /* if reset = 1 IDE reset will be asserted */
526 if (idereset)
527 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
528 else {
529 udelay (10000);
530 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
531 }
532}
533
534
535/* ------------------------------------------------------------------------- */
536
wdenkf3e0de62003-06-04 15:05:30 +0000537void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
wdenk858b1a62002-09-30 16:12:23 +0000538{
wdenkf3e0de62003-06-04 15:05:30 +0000539#if !defined(CONFIG_MIP405T)
540 unsigned char bc,rc,tmp;
wdenk858b1a62002-09-30 16:12:23 +0000541 int i;
wdenk858b1a62002-09-30 16:12:23 +0000542
wdenkf3e0de62003-06-04 15:05:30 +0000543 bc = in8 (PLD_BOARD_CFG_REG);
544 tmp = ~bc;
545 tmp &= 0xf;
wdenk858b1a62002-09-30 16:12:23 +0000546 rc = 0;
547 for (i = 0; i < 4; i++) {
548 rc <<= 1;
wdenkf3e0de62003-06-04 15:05:30 +0000549 rc += (tmp & 0x1);
550 tmp >>= 1;
wdenk858b1a62002-09-30 16:12:23 +0000551 }
552 rc++;
wdenk33149b82003-05-23 11:38:58 +0000553 if((((bc>>4) & 0xf)==0x1) /* Rev B PCB with */
554 && (rc==0x1)) /* Population Option 1 is a -3 */
555 rc=3;
wdenkf3e0de62003-06-04 15:05:30 +0000556 *pcbrev=(bc >> 4) & 0xf;
557 *var=rc;
558#else
559 unsigned char bc;
560 bc = in8 (PLD_BOARD_CFG_REG);
561 *pcbrev=(bc >> 4) & 0xf;
wdenk27b207f2003-07-24 23:38:38 +0000562 *var=16-(bc & 0xf);
wdenkf3e0de62003-06-04 15:05:30 +0000563#endif
564}
565
566/*
567 * Check Board Identity:
568 */
569/* serial String: "MIP405_1000" OR "MIP405T_1000" */
570#if !defined(CONFIG_MIP405T)
571#define BOARD_NAME "MIP405"
572#else
573#define BOARD_NAME "MIP405T"
574#endif
575
576int checkboard (void)
577{
578 unsigned char s[50];
579 unsigned char bc, var;
580 int i;
581 backup_t *b = (backup_t *) s;
582
583 puts ("Board: ");
584 get_pcbrev_var(&bc,&var);
wdenk858b1a62002-09-30 16:12:23 +0000585 i = getenv_r ("serial#", s, 32);
wdenkf3e0de62003-06-04 15:05:30 +0000586 if ((i == 0) || strncmp (s, BOARD_NAME,sizeof(BOARD_NAME))) {
wdenk858b1a62002-09-30 16:12:23 +0000587 get_backup_values (b);
588 if (strncmp (b->signature, "MPL\0", 4) != 0) {
wdenkf3e0de62003-06-04 15:05:30 +0000589 puts ("### No HW ID - assuming " BOARD_NAME);
590 printf ("-%d Rev %c", var, 'A' + bc);
wdenk858b1a62002-09-30 16:12:23 +0000591 } else {
wdenkf3e0de62003-06-04 15:05:30 +0000592 b->serial_name[sizeof(BOARD_NAME)-1] = 0;
593 printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
594 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
wdenk858b1a62002-09-30 16:12:23 +0000595 }
596 } else {
wdenkf3e0de62003-06-04 15:05:30 +0000597 s[sizeof(BOARD_NAME)-1] = 0;
598 printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
599 &s[sizeof(BOARD_NAME)]);
wdenk858b1a62002-09-30 16:12:23 +0000600 }
601 bc = in8 (PLD_EXT_CONF_REG);
602 printf (" Boot Config: 0x%x\n", bc);
603 return (0);
604}
605
606
607/* ------------------------------------------------------------------------- */
608/* ------------------------------------------------------------------------- */
609/*
610 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
611 the necessary info for SDRAM controller configuration
612*/
613/* ------------------------------------------------------------------------- */
614/* ------------------------------------------------------------------------- */
615static int test_dram (unsigned long ramsize);
616
617long int initdram (int board_type)
618{
619
620 unsigned long bank_reg[4], tmp, bank_size;
621 int i, ds;
622 unsigned long TotalSize;
623
624 ds = 0;
625 /* since the DRAM controller is allready set up, calculate the size with the
626 bank registers */
627 mtdcr (memcfga, mem_mb0cf);
628 bank_reg[0] = mfdcr (memcfgd);
629 mtdcr (memcfga, mem_mb1cf);
630 bank_reg[1] = mfdcr (memcfgd);
631 mtdcr (memcfga, mem_mb2cf);
632 bank_reg[2] = mfdcr (memcfgd);
633 mtdcr (memcfga, mem_mb3cf);
634 bank_reg[3] = mfdcr (memcfgd);
635 TotalSize = 0;
636 for (i = 0; i < 4; i++) {
637 if ((bank_reg[i] & 0x1) == 0x1) {
638 tmp = (bank_reg[i] >> 17) & 0x7;
639 bank_size = 4 << tmp;
640 TotalSize += bank_size;
641 } else
642 ds = 1;
643 }
644 mtdcr (memcfga, mem_ecccf);
645 tmp = mfdcr (memcfgd);
646
647 if (!tmp)
648 printf ("No ");
649 printf ("ECC ");
650
651 test_dram (TotalSize * MEGA_BYTE);
652 return (TotalSize * MEGA_BYTE);
653}
654
655/* ------------------------------------------------------------------------- */
656
wdenk858b1a62002-09-30 16:12:23 +0000657
658static int test_dram (unsigned long ramsize)
659{
660#ifdef SDRAM_DEBUG
661 mem_test (0L, ramsize, 1);
662#endif
663 /* not yet implemented */
664 return (1);
665}
666
wdenk27b207f2003-07-24 23:38:38 +0000667/* used to check if the time in RTC is valid */
668static unsigned long start;
669static struct rtc_time tm;
670
wdenk858b1a62002-09-30 16:12:23 +0000671int misc_init_r (void)
672{
wdenk27b207f2003-07-24 23:38:38 +0000673 /* check, if RTC is running */
674 rtc_get (&tm);
675 start=get_timer(0);
wdenkf3e0de62003-06-04 15:05:30 +0000676 /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
677 if (mfdcr(strap) & PSR_ROM_LOC)
678 mtspr(ccr0, (mfspr(ccr0) & ~0x80));
679
wdenk858b1a62002-09-30 16:12:23 +0000680 return (0);
681}
682
683
684void print_mip405_rev (void)
685{
wdenkf3e0de62003-06-04 15:05:30 +0000686 unsigned char part, vers, pcbrev, var;
wdenk858b1a62002-09-30 16:12:23 +0000687
wdenkf3e0de62003-06-04 15:05:30 +0000688 get_pcbrev_var(&pcbrev,&var);
wdenk858b1a62002-09-30 16:12:23 +0000689 part = in8 (PLD_PART_REG);
690 vers = in8 (PLD_VERS_REG);
wdenkf3e0de62003-06-04 15:05:30 +0000691 printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
692 var, pcbrev + 'A', part & 0x7F, vers);
wdenk858b1a62002-09-30 16:12:23 +0000693}
694
wdenk33149b82003-05-23 11:38:58 +0000695extern void mem_test_reloc(void);
wdenk27b207f2003-07-24 23:38:38 +0000696extern int mk_date (char *, struct rtc_time *);
wdenk858b1a62002-09-30 16:12:23 +0000697
698int last_stage_init (void)
699{
wdenk27b207f2003-07-24 23:38:38 +0000700 unsigned long stop;
701 struct rtc_time newtm;
702 unsigned char *s;
wdenk33149b82003-05-23 11:38:58 +0000703 mem_test_reloc();
wdenk3e386912003-04-05 00:53:31 +0000704 /* write correct LED configuration */
wdenk858b1a62002-09-30 16:12:23 +0000705 if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
706 printf ("Error writing to the PHY\n");
707 }
wdenk3e386912003-04-05 00:53:31 +0000708 /* since LED/CFG2 is not connected on the -2,
709 * write to correct capability information */
710 if (miiphy_write (0x1, 0x4, 0x01E1) != 0) {
711 printf ("Error writing to the PHY\n");
712 }
wdenk858b1a62002-09-30 16:12:23 +0000713 print_mip405_rev ();
714 show_stdio_dev ();
715 check_env ();
wdenk27b207f2003-07-24 23:38:38 +0000716 /* check if RTC time is valid */
717 stop=get_timer(start);
718 while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */
719 udelay(1000);
720 stop=get_timer(start);
721 }
722 rtc_get (&newtm);
723 if(tm.tm_sec==newtm.tm_sec) {
724 s=getenv("defaultdate");
725 if(!s)
726 mk_date ("010112001970", &newtm);
727 else
728 if(mk_date (s, &newtm)!=0) {
729 printf("RTC: Bad date format in defaultdate\n");
730 return 0;
731 }
732 rtc_reset ();
733 rtc_set(&newtm);
734 }
wdenk858b1a62002-09-30 16:12:23 +0000735 return 0;
736}
737
738/***************************************************************************
739 * some helping routines
740 */
741
742int overwrite_console (void)
743{
744 return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */
745}
746
747
748/************************************************************************
749* Print MIP405 Info
750************************************************************************/
751void print_mip405_info (void)
752{
753 unsigned char part, vers, cfg, irq_reg, com_mode, ext;
754
755 part = in8 (PLD_PART_REG);
756 vers = in8 (PLD_VERS_REG);
757 cfg = in8 (PLD_BOARD_CFG_REG);
758 irq_reg = in8 (PLD_IRQ_REG);
759 com_mode = in8 (PLD_COM_MODE_REG);
760 ext = in8 (PLD_EXT_CONF_REG);
761
wdenkf3e0de62003-06-04 15:05:30 +0000762 printf ("PLD Part %d version %d\n", part & 0x7F, vers);
wdenk858b1a62002-09-30 16:12:23 +0000763 printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
764 printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
765 (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
766 printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
767 printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
wdenkf3e0de62003-06-04 15:05:30 +0000768#if !defined(CONFIG_MIP405T)
wdenk858b1a62002-09-30 16:12:23 +0000769 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
770 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
771 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
772 (ext >> 6) & 0x1, (ext >> 7) & 0x1);
773 printf ("SER1 uses handshakes %s\n",
774 (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
wdenkf3e0de62003-06-04 15:05:30 +0000775#else
wdenk27b207f2003-07-24 23:38:38 +0000776 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
wdenkf3e0de62003-06-04 15:05:30 +0000777 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
778 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
wdenk27b207f2003-07-24 23:38:38 +0000779 (ext >> 6) & 0x1,(ext >> 7) & 0x1);
wdenkf3e0de62003-06-04 15:05:30 +0000780#endif
wdenk858b1a62002-09-30 16:12:23 +0000781 printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
782 printf ("IRQs:\n");
783 printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
wdenkf3e0de62003-06-04 15:05:30 +0000784#if !defined(CONFIG_MIP405T)
wdenk858b1a62002-09-30 16:12:23 +0000785 printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
786 printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
wdenkf3e0de62003-06-04 15:05:30 +0000787#endif
wdenk858b1a62002-09-30 16:12:23 +0000788 printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
789 printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
790 printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");
791}