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Stefan Roese899620c2006-08-15 14:22:35 +02001/*
Stefan Roese94627322008-03-19 10:23:43 +01002 * (C) Copyright 2006-2008
Stefan Roese899620c2006-08-15 14:22:35 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*-----------------------------------------------------------------------
28 * High Level Configuration Options
29 *----------------------------------------------------------------------*/
30#define CONFIG_ALPR 1 /* Board is ebony */
31#define CONFIG_440GX 1 /* Specifc GX support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020032#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roese899620c2006-08-15 14:22:35 +020033#define CONFIG_4xx 1 /* ... PPC4xx family */
34#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Stefan Roese1c2ce222006-11-27 14:12:17 +010035#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
Stefan Roese1c2ce222006-11-27 14:12:17 +010036#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +010037#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
Stefan Roese899620c2006-08-15 14:22:35 +020038
39/*-----------------------------------------------------------------------
40 * Base addresses -- Note these are effective addresses where the
41 * actual resources get mapped (not physical addresses)
42 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
44#define CONFIG_SYS_FLASH_BASE 0xffe00000 /* start of FLASH */
45#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
46#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
47#define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
48#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
49#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
50#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
51#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
52#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
53#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roese899620c2006-08-15 14:22:35 +020054
55
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
57#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
Stefan Roese899620c2006-08-15 14:22:35 +020058
59/*-----------------------------------------------------------------------
60 * Initial RAM & stack pointer (placed in internal SRAM)
61 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_TEMP_STACK_OCM 1
63#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
64#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
65#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
66#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
Stefan Roese899620c2006-08-15 14:22:35 +020067
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
69#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
70#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
Stefan Roese899620c2006-08-15 14:22:35 +020071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
73#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
Stefan Roese899620c2006-08-15 14:22:35 +020074
75/*-----------------------------------------------------------------------
76 * Serial Port
77 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Stefan Roese899620c2006-08-15 14:22:35 +020079#define CONFIG_BAUDRATE 115200
80#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
81
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roese899620c2006-08-15 14:22:35 +020083 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
84
85/*-----------------------------------------------------------------------
Stefan Roese899620c2006-08-15 14:22:35 +020086 * FLASH related
87 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020089#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
91#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
92#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
93#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
94#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Stefan Roese899620c2006-08-15 14:22:35 +020095
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020096#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese899620c2006-08-15 14:22:35 +020097
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020098#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200100#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese899620c2006-08-15 14:22:35 +0200101
102/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200103#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
104#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese899620c2006-08-15 14:22:35 +0200105
106/*-----------------------------------------------------------------------
107 * DDR SDRAM
108 *----------------------------------------------------------------------*/
109#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
110#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
111#undef CONFIG_SDRAM_ECC /* enable ECC support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_SDRAM_TABLE { \
Stefan Roese899620c2006-08-15 14:22:35 +0200113 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
114 {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
115
116/*-----------------------------------------------------------------------
117 * I2C
118 *----------------------------------------------------------------------*/
119#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
120#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
122#define CONFIG_SYS_I2C_SLAVE 0x7F
123#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Stefan Roese899620c2006-08-15 14:22:35 +0200124
125/*-----------------------------------------------------------------------
126 * I2C EEPROM (PCF8594C)
127 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
129#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roese899620c2006-08-15 14:22:35 +0200130/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
132#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
Stefan Roese899620c2006-08-15 14:22:35 +0200133 /* 8 byte page write mode using */
134 /* last 3 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
Stefan Roese899620c2006-08-15 14:22:35 +0200136
137#define CONFIG_PREBOOT "echo;" \
Stefan Roese63044302007-01-30 12:51:07 +0100138 "echo Type \"run kernelx\" to boot the system;" \
Stefan Roese899620c2006-08-15 14:22:35 +0200139 "echo"
140
141#undef CONFIG_BOOTARGS
142
143#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100144 "netdev=eth3\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200145 "hostname=alpr\0" \
Stefan Roese94627322008-03-19 10:23:43 +0100146 "fdt_file=alpr/alpr.dtb\0" \
147 "fdt_addr=400000\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200148 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Stefan Roese63044302007-01-30 12:51:07 +0100149 "nfsroot=${serverip}:${rootpath} ${init}\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200150 "ramargs=setenv bootargs root=/dev/ram rw\0" \
151 "addip=setenv bootargs ${bootargs} " \
152 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
153 ":${hostname}:${netdev}:off panic=1\0" \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100154 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
155 "mem=193M\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200156 "flash_nfs=run nfsargs addip addtty;" \
157 "bootm ${kernel_addr}\0" \
158 "flash_self=run ramargs addip addtty;" \
159 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
160 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
161 "bootm\0" \
Stefan Roese94627322008-03-19 10:23:43 +0100162 "net_nfs_fdt=tftp 200000 ${bootfile};" \
163 "tftp ${fdt_addr} ${fdt_file};" \
164 "run nfsargs addip addtty;" \
165 "bootm 200000 - ${fdt_addr}\0" \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100166 "rootpath=/opt/projects/alpr/nfs_root\0" \
167 "bootfile=/alpr/uImage\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200168 "kernel_addr=fff00000\0" \
169 "ramdisk_addr=fff10000\0" \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100170 "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200171 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
172 "cp.b 100000 fffc0000 40000;" \
173 "setenv filesize;saveenv\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100174 "upd=run load update\0" \
Stefan Roesef16c1da2007-01-06 15:56:13 +0100175 "ethprime=ppc_4xx_eth3\0" \
176 "ethact=ppc_4xx_eth3\0" \
177 "autoload=no\0" \
178 "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
Stefan Roesef16c1da2007-01-06 15:56:13 +0100179 "load_fpga=fpga load 0 ffe00000 10dd9a\0" \
180 "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
181 "rootfstype=jffs2 init=/sbin/init\0" \
182 "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
183 ";bootm 200000\0" \
184 "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
185 "addtty;bootm 200000\0" \
Stefan Roese63044302007-01-30 12:51:07 +0100186 "kernel1=setenv actkernel 'kernel1';run load_fpga " \
187 "kernel1_mtd\0" \
188 "kernel2=setenv actkernel 'kernel2';run load_fpga " \
189 "kernel2_mtd\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200190 ""
Stefan Roesef16c1da2007-01-06 15:56:13 +0100191
192#define CONFIG_BOOTCOMMAND "run kernel2"
Stefan Roese899620c2006-08-15 14:22:35 +0200193
Stefan Roese1c2ce222006-11-27 14:12:17 +0100194#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
Stefan Roese899620c2006-08-15 14:22:35 +0200195
196#define CONFIG_BAUDRATE 115200
197
198#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roese899620c2006-08-15 14:22:35 +0200200
Ben Warren96e21f82008-10-27 23:50:15 -0700201#define CONFIG_PPC4xx_EMAC
Stefan Roese899620c2006-08-15 14:22:35 +0200202#define CONFIG_MII 1 /* MII PHY management */
203#define CONFIG_NET_MULTI 1
204#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
205#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100206#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */
207#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */
Stefan Roese899620c2006-08-15 14:22:35 +0200208#define CONFIG_HAS_ETH0
209#define CONFIG_HAS_ETH1
210#define CONFIG_HAS_ETH2
211#define CONFIG_HAS_ETH3
212#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Stefan Roeseec0c2ec2006-11-27 14:46:06 +0100213#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/
Stefan Roese899620c2006-08-15 14:22:35 +0200214#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Stefan Roese899620c2006-08-15 14:22:35 +0200216
Stefan Roese5bc528f2006-10-07 11:35:25 +0200217#define CONFIG_NETCONSOLE /* include NetConsole support */
218
Stefan Roese899620c2006-08-15 14:22:35 +0200219
Jon Loeliger0b361c92007-07-04 22:31:42 -0500220/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500221 * BOOTP options
222 */
223#define CONFIG_BOOTP_BOOTFILESIZE
224#define CONFIG_BOOTP_BOOTPATH
225#define CONFIG_BOOTP_GATEWAY
226#define CONFIG_BOOTP_HOSTNAME
227
228
229/*
Jon Loeliger0b361c92007-07-04 22:31:42 -0500230 * Command line configuration.
231 */
232#include <config_cmd_default.h>
233
Jon Loeliger0b361c92007-07-04 22:31:42 -0500234#define CONFIG_CMD_DHCP
Jon Loeliger0b361c92007-07-04 22:31:42 -0500235#define CONFIG_CMD_EEPROM
Jon Loeliger0b361c92007-07-04 22:31:42 -0500236#define CONFIG_CMD_FPGA
237#define CONFIG_CMD_I2C
Jon Loeliger0b361c92007-07-04 22:31:42 -0500238#define CONFIG_CMD_MII
239#define CONFIG_CMD_NAND
240#define CONFIG_CMD_NET
Jon Loeliger0b361c92007-07-04 22:31:42 -0500241#define CONFIG_CMD_PCI
Stefan Roese8c92af72008-12-09 20:08:01 +0100242#undef CONFIG_CMD_NFS
Stefan Roese899620c2006-08-15 14:22:35 +0200243
244#undef CONFIG_WATCHDOG /* watchdog disabled */
245
246/*
247 * Miscellaneous configurable options
248 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_LONGHELP /* undef to save memory */
250#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger0b361c92007-07-04 22:31:42 -0500251#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese899620c2006-08-15 14:22:35 +0200253#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese899620c2006-08-15 14:22:35 +0200255#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
257#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
258#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese899620c2006-08-15 14:22:35 +0200259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_ALT_MEMTEST 1 /* Enable more extensive memtest*/
261#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
262#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roese899620c2006-08-15 14:22:35 +0200263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
265#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roese899620c2006-08-15 14:22:35 +0200266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roese899620c2006-08-15 14:22:35 +0200268
Stefan Roese5bc528f2006-10-07 11:35:25 +0200269#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Stefan Roese899620c2006-08-15 14:22:35 +0200270#define CONFIG_LOOPW 1 /* enable loopw command */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200271#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Stefan Roese899620c2006-08-15 14:22:35 +0200272#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100273#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
Stefan Roese899620c2006-08-15 14:22:35 +0200276
Stefan Roese899620c2006-08-15 14:22:35 +0200277/*-----------------------------------------------------------------------
278 * PCI stuff
279 *-----------------------------------------------------------------------
280 */
281/* General PCI */
282#define CONFIG_PCI /* include pci support */
283#define CONFIG_PCI_PNP /* do pci plug-and-play */
284#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100286#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
Stefan Roese899620c2006-08-15 14:22:35 +0200287
288/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
290#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese899620c2006-08-15 14:22:35 +0200291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
293#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Stefan Roese899620c2006-08-15 14:22:35 +0200294
295/*-----------------------------------------------------------------------
296 * FPGA stuff
Stefan Roese1c2ce222006-11-27 14:12:17 +0100297 *-----------------------------------------------------------------------*/
Matthias Fuchs01335022007-12-27 17:12:34 +0100298#define CONFIG_FPGA
299#define CONFIG_FPGA_ALTERA
300#define CONFIG_FPGA_CYCLON2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_FPGA_CHECK_CTRLC
302#define CONFIG_SYS_FPGA_PROG_FEEDBACK
Stefan Roese899620c2006-08-15 14:22:35 +0200303#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
304 Reihe geschaltet -> sollte gehen,
305 aufpassen mit Datasize ist jetzt
306 halt doppelt so gross ... Seite 306
307 ist das mit den multiple Device in PS
308 Mode erklaert ...*/
309
Stefan Roese899620c2006-08-15 14:22:35 +0200310/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
312#define CONFIG_SYS_GPIO_DATA 19 /* FPGA data pin (cpu output) */
313#define CONFIG_SYS_GPIO_STATUS 20 /* FPGA status pin (cpu input) */
314#define CONFIG_SYS_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */
315#define CONFIG_SYS_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */
Stefan Roese899620c2006-08-15 14:22:35 +0200316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_GPIO_SEL_DPR 14 /* cpu output */
318#define CONFIG_SYS_GPIO_SEL_AVR 15 /* cpu output */
319#define CONFIG_SYS_GPIO_PROG_EN 23 /* cpu output */
Stefan Roese899620c2006-08-15 14:22:35 +0200320
Stefan Roese1c2ce222006-11-27 14:12:17 +0100321/*-----------------------------------------------------------------------
322 * Definitions for GPIO setup
323 *-----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_GPIO_SHUTDOWN (0x80000000 >> 6)
325#define CONFIG_SYS_GPIO_SSD_EMPTY (0x80000000 >> 9)
326#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 26)
327#define CONFIG_SYS_GPIO_REV0 (0x80000000 >> 14)
328#define CONFIG_SYS_GPIO_REV1 (0x80000000 >> 15)
Stefan Roese1c2ce222006-11-27 14:12:17 +0100329
330/*-----------------------------------------------------------------------
Stefan Roese899620c2006-08-15 14:22:35 +0200331 * NAND-FLASH stuff
Stefan Roese1c2ce222006-11-27 14:12:17 +0100332 *-----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_MAX_NAND_DEVICE 4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
335#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
336 CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
337#define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
Stefan Roese899620c2006-08-15 14:22:35 +0200338
339/*-----------------------------------------------------------------------
340 * External Bus Controller (EBC) Setup
341 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
Stefan Roese899620c2006-08-15 14:22:35 +0200343
344/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_EBC_PB0AP 0x92015480
346#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
Stefan Roese899620c2006-08-15 14:22:35 +0200347
Stefan Roese5bc528f2006-10-07 11:35:25 +0200348/* Memory Bank 1 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_EBC_PB1AP 0x01840380 /* TWT=3 */
350#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
Stefan Roese899620c2006-08-15 14:22:35 +0200351
352/*
353 * For booting Linux, the board info and command line data
354 * have to be in the first 8 MB of memory, since this is
355 * the maximum mapped by the Linux kernel during initialization.
356 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese899620c2006-08-15 14:22:35 +0200358
359/*
360 * Internal Definitions
361 *
362 * Boot Flags
363 */
364#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
365#define BOOTFLAG_WARM 0x02 /* Software reboot */
366
Jon Loeliger0b361c92007-07-04 22:31:42 -0500367#if defined(CONFIG_CMD_KGDB)
Stefan Roese899620c2006-08-15 14:22:35 +0200368#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
369#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
370#endif
Stefan Roese94627322008-03-19 10:23:43 +0100371
372/* pass open firmware flat tree */
373#define CONFIG_OF_LIBFDT 1
374#define CONFIG_OF_BOARD_SETUP 1
375
Stefan Roese899620c2006-08-15 14:22:35 +0200376#endif /* __CONFIG_H */