Blame - board/amcc/sequoia/sdram.h - github/trini/u-boot

Stefan Roese

0238898

2007-01-05 10:38:05 +0100

[diff] [blame]

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/*

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* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com

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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com

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* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com

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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com

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* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com

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*

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* This program is free software; you can redistribute it and/or

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* modify it under the terms of the GNU General Public License as

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* published by the Free Software Foundation; either version 2 of

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* the License, or (at your option) any later version.

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*

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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*

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* You should have received a copy of the GNU General Public License

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* along with this program; if not, write to the Free Software

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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,

* MA 02111-1307 USA

*/

#ifndef _SPD_SDRAM_DENALI_H_

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#define _SPD_SDRAM_DENALI_H_

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#define ppcMsync sync

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#define ppcMbar eieio

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/* General definitions */

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#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */

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#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */

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#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */

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#define SDRAM_NONE 0 /* No DIMM detected in Slot */

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#define MAXRANKS 2 /* 2 ranks maximum */

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/* Supported PLB Frequencies */

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#define PLB_FREQ_133MHZ 133333333

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#define PLB_FREQ_152MHZ 152000000

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#define PLB_FREQ_160MHZ 160000000

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#define PLB_FREQ_166MHZ 166666666

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/* Denali Core Registers */

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#define SDRAM_DCR_BASE 0x10

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#define DDR_DCR_BASE 0x10

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#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */

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#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */

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/*-----------------------------------------------------------------------------+

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| Values for ddrcfga register - indirect addressing of these regs

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+-----------------------------------------------------------------------------*/

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#define DDR0_00 0x00

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#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */

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#define DDR0_00_INT_ACK_ALL 0x7F000000

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#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)

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#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)

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/* Status */

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#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */

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/* Bit0. A single access outside the defined PHYSICAL memory space detected. */

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#define DDR0_00_INT_STATUS_BIT0 0x00010000

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/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */

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#define DDR0_00_INT_STATUS_BIT1 0x00020000

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/* Bit2. Single correctable ECC event detected */

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#define DDR0_00_INT_STATUS_BIT2 0x00040000

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/* Bit3. Multiple correctable ECC events detected. */

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#define DDR0_00_INT_STATUS_BIT3 0x00080000

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/* Bit4. Single uncorrectable ECC event detected. */

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#define DDR0_00_INT_STATUS_BIT4 0x00100000

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/* Bit5. Multiple uncorrectable ECC events detected. */

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#define DDR0_00_INT_STATUS_BIT5 0x00200000

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/* Bit6. DRAM initialization complete. */

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#define DDR0_00_INT_STATUS_BIT6 0x00400000

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/* Bit7. Logical OR of all lower bits. */

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#define DDR0_00_INT_STATUS_BIT7 0x00800000

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#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)

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#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)

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#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00

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#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)

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#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)

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#define DDR0_00_DLL_START_POINT_MASK 0x0000007F

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#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)

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#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)

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Stefan Roese

0238898

2007-01-05 10:38:05 +0100

[diff] [blame]

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#define DDR0_01 0x01

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#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000

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#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)

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#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)

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#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000

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#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)

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#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)

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#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */

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#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)

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#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)

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#define DDR0_01_INT_MASK_MASK 0x000000FF

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#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)

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#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)

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#define DDR0_01_INT_MASK_ALL_ON 0x000000FF

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#define DDR0_01_INT_MASK_ALL_OFF 0x00000000

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#define DDR0_02 0x02

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#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */

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#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)

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#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)

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#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */

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#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)

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#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)

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#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */

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#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)

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#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)

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#define DDR0_02_START_MASK 0x00000001

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#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)

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#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)

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#define DDR0_02_START_OFF 0x00000000

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#define DDR0_02_START_ON 0x00000001

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#define DDR0_03 0x03

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#define DDR0_03_BSTLEN_MASK 0x07000000

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#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)

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#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)

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#define DDR0_03_CASLAT_MASK 0x00070000

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#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)

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#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)

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#define DDR0_03_CASLAT_LIN_MASK 0x00000F00

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#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)

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#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)

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#define DDR0_03_INITAREF_MASK 0x0000000F

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#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)

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#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)

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#define DDR0_04 0x04

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#define DDR0_04_TRC_MASK 0x1F000000

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#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)

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#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)

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#define DDR0_04_TRRD_MASK 0x00070000

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#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)

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#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)

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#define DDR0_04_TRTP_MASK 0x00000700

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#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)

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#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)

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#define DDR0_05 0x05

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#define DDR0_05_TMRD_MASK 0x1F000000

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#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)

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#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)

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#define DDR0_05_TEMRS_MASK 0x00070000

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#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)

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#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)

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#define DDR0_05_TRP_MASK 0x00000F00

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#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)

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#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)

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#define DDR0_05_TRAS_MIN_MASK 0x000000FF

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#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)

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#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)

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#define DDR0_06 0x06

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#define DDR0_06_WRITEINTERP_MASK 0x01000000

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#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)

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#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)

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#define DDR0_06_TWTR_MASK 0x00070000

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#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)

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#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)

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#define DDR0_06_TDLL_MASK 0x0000FF00

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#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)

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#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)

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#define DDR0_06_TRFC_MASK 0x0000007F

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#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)

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#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)

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#define DDR0_07 0x07

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#define DDR0_07_NO_CMD_INIT_MASK 0x01000000

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#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)

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#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)

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#define DDR0_07_TFAW_MASK 0x001F0000

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#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)

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#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)

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#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100

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#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)

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#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)

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#define DDR0_07_AREFRESH_MASK 0x00000001

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#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)

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#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)

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#define DDR0_08 0x08

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#define DDR0_08_WRLAT_MASK 0x07000000

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#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)

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#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)

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#define DDR0_08_TCPD_MASK 0x00FF0000

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#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)

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#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)

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#define DDR0_08_DQS_N_EN_MASK 0x00000100

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#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)

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#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)

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#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001

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#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)

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#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)

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#define DDR0_09 0x09

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#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000

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#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)

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#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)

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#define DDR0_09_RTT_0_MASK 0x00030000

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#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)

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#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)

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#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00

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#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)

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#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)

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#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F

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#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)

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#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)

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#define DDR0_10 0x0A

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#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */

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#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)

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#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)

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#define DDR0_10_CS_MAP_MASK 0x00000300

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#define DDR0_10_CS_MAP_NO_MEM 0x00000000

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#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100

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#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200

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#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)

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#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)

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#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F

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#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)

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#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)

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#define DDR0_11 0x0B

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#define DDR0_11_SREFRESH_MASK 0x01000000

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#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)

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#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)

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#define DDR0_11_TXSNR_MASK 0x00FF0000

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#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)

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#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)

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#define DDR0_11_TXSR_MASK 0x0000FF00

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#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)

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#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)

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#define DDR0_12 0x0C

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#define DDR0_12_TCKE_MASK 0x0000007

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#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)

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#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)

#define DDR0_13 0x0D

#define DDR0_14 0x0E

#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000

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#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)

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#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)

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#define DDR0_14_REDUC_MASK 0x00010000

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#define DDR0_14_REDUC_64BITS 0x00000000

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#define DDR0_14_REDUC_32BITS 0x00010000

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#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)

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#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)

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#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100

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#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)

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#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)

#define DDR0_15 0x0F

#define DDR0_16 0x10

#define DDR0_17 0x11

#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000

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#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)

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#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)

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#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */

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#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000

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#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000

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#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)

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#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)

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#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */

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#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)

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#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)

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#define DDR0_18 0x12

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#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F

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#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000

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#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)

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#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)

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#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000

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#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)

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#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)

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#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00

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#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)

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#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)

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#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F

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#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)

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#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)

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#define DDR0_19 0x13

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#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F

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#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000

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#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)

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#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)

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#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000

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#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)

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#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)

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#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00

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#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)

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#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)

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#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F

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#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)

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#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)

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#define DDR0_20 0x14

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#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000

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#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)

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#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)

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#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000

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#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)

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#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)

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#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00

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#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)

317

#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)

318

#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F

319

#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)

320

#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)

321

322

#define DDR0_21 0x15

323

#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000

324

#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)

325

#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)

326

#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000

327

#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)

328

#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)

329

#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00

330

#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)

331

#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)

332

#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F

333

#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)

334

#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)

#define DDR0_22 0x16

/* ECC */

#define DDR0_22_CTRL_RAW_MASK 0x03000000

339

#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */

340

#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/

341

#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */

342

#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */

343

#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)

344

#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)

345

346

#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000

347

#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)

348

#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)

349

#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00

350

#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)

351

#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)

352

#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F

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#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)

354

#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)

355

356

Stefan Roese

0238898

2007-01-05 10:38:05 +0100

[diff] [blame]

357

#define DDR0_23 0x17

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#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000

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#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)

360

#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)

361

#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */

362

#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)

363

#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)

364

#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */

365

#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)

366

#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)

367

#define DDR0_23_FWC_MASK 0x00000001 /* Write only */

368

#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)

369

#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)

370

371

#define DDR0_24 0x18

372

#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000

373

#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)

374

#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)

375

#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000

376

#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)

377

#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)

378

#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300

379

#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)

380

#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)

381

#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003

382

#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)

383

#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)

384

385

#define DDR0_25 0x19

386

#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */

387

#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)

388

#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)

389

#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */

390

#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)

391

#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)

392

393

#define DDR0_26 0x1A

394

#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000

395

#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)

396

#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)

397

#define DDR0_26_TREF_MASK 0x00003FFF

398

#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)

399

#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)

400

401

#define DDR0_27 0x1B

402

#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000

403

#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)

404

#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)

405

#define DDR0_27_TINIT_MASK 0x0000FFFF

406

#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)

407

#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)

408

409

#define DDR0_28 0x1C

410

#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000

411

#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)

412

#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)

413

#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF

414

#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)

415

#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)

#define DDR0_29 0x1D

#define DDR0_30 0x1E

#define DDR0_31 0x1F

#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF

423

#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)

424

#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)

425

426

#define DDR0_32 0x20

427

#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */

428

#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)

429

#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)

430

431

#define DDR0_33 0x21

432

#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */

433

#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)

434

#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)

435

436

#define DDR0_34 0x22

437

#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */

438

#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)

439

#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)

440

441

#define DDR0_35 0x23

442

#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */

443

#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)

444

#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)

445

446

#define DDR0_36 0x24

447

#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */

448

#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)

449

#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)

450

451

#define DDR0_37 0x25

452

#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */

453

#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)

454

#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)

455

456

#define DDR0_38 0x26

457

#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */

458

#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)

459

#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)

460

461

#define DDR0_39 0x27

462

#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */

463

#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)

464

#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)

465

466

#define DDR0_40 0x28

467

#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */

468

#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)

469

#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)

470

471

#define DDR0_41 0x29

472

#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */

473

#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)

474

#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)

475

476

#define DDR0_42 0x2A

477

#define DDR0_42_ADDR_PINS_MASK 0x07000000

478

#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)

479

#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)

480

#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F

481

#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)

482

#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)

483

484

#define DDR0_43 0x2B

485

#define DDR0_43_TWR_MASK 0x07000000

486

#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)

487

#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)

488

#define DDR0_43_APREBIT_MASK 0x000F0000

489

#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)

490

#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)

491

#define DDR0_43_COLUMN_SIZE_MASK 0x00000700

492

#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)

493

#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)

494

#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001

495

#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001

496

#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000

497

#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)

498

#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)

499

500

#define DDR0_44 0x2C

501

#define DDR0_44_TRCD_MASK 0x000000FF

502

#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)

503

#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)

504

505

#endif /* _SPD_SDRAM_DENALI_H_ */