| Siva Durga Prasad Paladugu | 0b54a9d | 2015-06-10 15:50:57 +0530 | [diff] [blame] | 1 | /* |
| Michal Simek | d041e3e | 2015-08-20 15:21:48 +0200 | [diff] [blame] | 2 | * Configuration for Xilinx ZynqMP emulation platforms |
| Siva Durga Prasad Paladugu | 0b54a9d | 2015-06-10 15:50:57 +0530 | [diff] [blame] | 3 | * |
| 4 | * (C) Copyright 2014 - 2015 Xilinx, Inc. |
| 5 | * Michal Simek <michal.simek@xilinx.com> |
| 6 | * Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
| 7 | * |
| 8 | * Based on Configuration for Versatile Express |
| 9 | * |
| 10 | * SPDX-License-Identifier: GPL-2.0+ |
| 11 | */ |
| 12 | |
| 13 | #ifndef __CONFIG_ZYNQMP_EP_H |
| 14 | #define __CONFIG_ZYNQMP_EP_H |
| 15 | |
| Michal Simek | f3bd728 | 2015-09-29 01:27:13 +0200 | [diff] [blame] | 16 | #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 |
| Siva Durga Prasad Paladugu | c061d5b | 2016-01-05 12:21:05 +0530 | [diff] [blame] | 17 | #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) |
| Siva Durga Prasad Paladugu | 0b54a9d | 2015-06-10 15:50:57 +0530 | [diff] [blame] | 18 | #define CONFIG_ZYNQ_EEPROM |
| Alexander Graf | 3bac830 | 2016-07-21 01:34:00 +0200 | [diff] [blame] | 19 | #define CONFIG_SATA_CEVA |
| Siva Durga Prasad Paladugu | f4dd69c | 2015-11-16 16:49:23 +0530 | [diff] [blame] | 20 | #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ |
| 21 | ZYNQMP_USB1_XHCI_BASEADDR} |
| Siva Durga Prasad Paladugu | 0b54a9d | 2015-06-10 15:50:57 +0530 | [diff] [blame] | 22 | |
| Michal Simek | 713b616 | 2015-11-05 08:32:14 +0100 | [diff] [blame] | 23 | #define COUNTER_FREQUENCY 4000000 |
| 24 | |
| Siva Durga Prasad Paladugu | 0b54a9d | 2015-06-10 15:50:57 +0530 | [diff] [blame] | 25 | #include <configs/xilinx_zynqmp.h> |
| 26 | |
| 27 | #endif /* __CONFIG_ZYNQMP_EP_H */ |