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Matt Waddelb80e41a2010-10-07 15:48:45 -06001/*
Ryan Harkincd4f46e2013-04-09 02:20:31 +00002 * (C) Copyright 2011 ARM Limited
Matt Waddelb80e41a2010-10-07 15:48:45 -06003 * (C) Copyright 2010 Linaro
4 * Matt Waddel, <matt.waddel@linaro.org>
5 *
6 * Configuration for Versatile Express. Parts were derived from other ARM
7 * configurations.
8 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02009 * SPDX-License-Identifier: GPL-2.0+
Matt Waddelb80e41a2010-10-07 15:48:45 -060010 */
11
Ryan Harkincd4f46e2013-04-09 02:20:31 +000012#ifndef __VEXPRESS_COMMON_H
13#define __VEXPRESS_COMMON_H
14
15/*
16 * Definitions copied from linux kernel:
17 * arch/arm/mach-vexpress/include/mach/motherboard.h
18 */
19#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
20/* CS register bases for the original memory map. */
21#define V2M_PA_CS0 0x40000000
22#define V2M_PA_CS1 0x44000000
23#define V2M_PA_CS2 0x48000000
24#define V2M_PA_CS3 0x4c000000
25#define V2M_PA_CS7 0x10000000
26
27#define V2M_PERIPH_OFFSET(x) (x << 12)
28#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
29#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
30#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
31
32#define V2M_BASE 0x60000000
33#define CONFIG_SYS_TEXT_BASE 0x60800000
34#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
35/* CS register bases for the extended memory map. */
36#define V2M_PA_CS0 0x08000000
37#define V2M_PA_CS1 0x0c000000
38#define V2M_PA_CS2 0x14000000
39#define V2M_PA_CS3 0x18000000
40#define V2M_PA_CS7 0x1c000000
41
42#define V2M_PERIPH_OFFSET(x) (x << 16)
43#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
44#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
45#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
46
47#define V2M_BASE 0x80000000
48#define CONFIG_SYS_TEXT_BASE 0x80800000
49#endif
50
51/*
52 * Physical addresses, offset from V2M_PA_CS0-3
53 */
54#define V2M_NOR0 (V2M_PA_CS0)
55#define V2M_NOR1 (V2M_PA_CS1)
56#define V2M_SRAM (V2M_PA_CS2)
57#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
58#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000)
59#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
60
61/* Common peripherals relative to CS7. */
62#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
63#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
64#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
65#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
66
67#define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
68#define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
69#define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
70#define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
71
72#define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
73
74#define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
75#define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
76
77#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
78#define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
79
80#define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
81
82#define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
83#define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32)
84
85/* System register offsets. */
86#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
87#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
88#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
89
90/*
91 * Configuration
92 */
93#define SYS_CFG_START (1 << 31)
94#define SYS_CFG_WRITE (1 << 30)
95#define SYS_CFG_OSC (1 << 20)
96#define SYS_CFG_VOLT (2 << 20)
97#define SYS_CFG_AMP (3 << 20)
98#define SYS_CFG_TEMP (4 << 20)
99#define SYS_CFG_RESET (5 << 20)
100#define SYS_CFG_SCC (6 << 20)
101#define SYS_CFG_MUXFPGA (7 << 20)
102#define SYS_CFG_SHUTDOWN (8 << 20)
103#define SYS_CFG_REBOOT (9 << 20)
104#define SYS_CFG_DVIMODE (11 << 20)
105#define SYS_CFG_POWER (12 << 20)
106#define SYS_CFG_SITE_MB (0 << 16)
107#define SYS_CFG_SITE_DB1 (1 << 16)
108#define SYS_CFG_SITE_DB2 (2 << 16)
109#define SYS_CFG_STACK(n) ((n) << 12)
110
111#define SYS_CFG_ERR (1 << 1)
112#define SYS_CFG_COMPLETE (1 << 0)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600113
114/* Board info register */
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000115#define SYS_ID V2M_SYSREGS
Matt Waddelb80e41a2010-10-07 15:48:45 -0600116#define CONFIG_REVISION_TAG 1
117
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000118#define CONFIG_SYS_MEMTEST_START V2M_BASE
Matt Waddelb80e41a2010-10-07 15:48:45 -0600119#define CONFIG_SYS_MEMTEST_END 0x20000000
Matt Waddelb80e41a2010-10-07 15:48:45 -0600120
121#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
122#define CONFIG_SETUP_MEMORY_TAGS 1
Aneesh Ve47f2db2011-06-16 23:30:48 +0000123#define CONFIG_SYS_L2CACHE_OFF 1
Matt Waddelb80e41a2010-10-07 15:48:45 -0600124#define CONFIG_INITRD_TAG 1
Chris Kuethe95617232015-01-21 20:52:33 -0800125#define CONFIG_SYS_GENERIC_BOARD
Grant Likely2fa8ca92011-03-28 09:59:07 +0000126#define CONFIG_OF_LIBFDT 1
127
Matt Waddelb80e41a2010-10-07 15:48:45 -0600128/* Size of malloc() pool */
129#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600130
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000131#define SCTL_BASE V2M_SYSCTL
Matt Waddelb80e41a2010-10-07 15:48:45 -0600132#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
133
Rob Herringb3a7f222013-10-04 10:22:45 -0500134#define CONFIG_SYS_TIMER_RATE 1000000
Ian Campbellcb7ee1b2013-11-17 15:17:42 +0000135#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
Rob Herringb3a7f222013-10-04 10:22:45 -0500136#define CONFIG_SYS_TIMER_COUNTS_DOWN
137
Matt Waddelb80e41a2010-10-07 15:48:45 -0600138/* SMSC9115 Ethernet from SMSC9118 family */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600139#define CONFIG_SMC911X 1
140#define CONFIG_SMC911X_32_BIT 1
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000141#define CONFIG_SMC911X_BASE V2M_LAN9118
Matt Waddelb80e41a2010-10-07 15:48:45 -0600142
143/* PL011 Serial Configuration */
144#define CONFIG_PL011_SERIAL
145#define CONFIG_PL011_CLOCK 24000000
146#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
147 (void *)CONFIG_SYS_SERIAL1}
148#define CONFIG_CONS_INDEX 0
149
150#define CONFIG_BAUDRATE 38400
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000151#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
152#define CONFIG_SYS_SERIAL0 V2M_UART0
153#define CONFIG_SYS_SERIAL1 V2M_UART1
Matt Waddelb80e41a2010-10-07 15:48:45 -0600154
155/* Command line configuration */
156#define CONFIG_CMD_BDI
157#define CONFIG_CMD_DHCP
Jason Hobbse21669f2011-08-23 11:07:00 +0000158#define CONFIG_CMD_PXE
159#define CONFIG_MENU
Matt Waddelb80e41a2010-10-07 15:48:45 -0600160#define CONFIG_CMD_ELF
161#define CONFIG_CMD_ENV
162#define CONFIG_CMD_FLASH
163#define CONFIG_CMD_IMI
164#define CONFIG_CMD_MEMORY
165#define CONFIG_CMD_NET
166#define CONFIG_CMD_PING
167#define CONFIG_CMD_SAVEENV
Matt Waddelb80e41a2010-10-07 15:48:45 -0600168#define CONFIG_CMD_RUN
Andre Przywarad21c3af2013-04-09 02:20:33 +0000169#define CONFIG_CMD_BOOTZ
170#define CONFIG_SUPPORT_RAW_INITRD
Matt Waddelb80e41a2010-10-07 15:48:45 -0600171
172#define CONFIG_CMD_FAT
173#define CONFIG_DOS_PARTITION 1
174#define CONFIG_MMC 1
175#define CONFIG_CMD_MMC
176#define CONFIG_GENERIC_MMC
Matt Waddelf0c64522011-04-16 11:54:08 +0000177#define CONFIG_ARM_PL180_MMCI
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000178#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI
Matt Waddelf0c64522011-04-16 11:54:08 +0000179#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
180#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
Matt Waddelb80e41a2010-10-07 15:48:45 -0600181
182/* BOOTP options */
183#define CONFIG_BOOTP_BOOTFILESIZE
184#define CONFIG_BOOTP_BOOTPATH
185#define CONFIG_BOOTP_GATEWAY
186#define CONFIG_BOOTP_HOSTNAME
Jason Hobbse72f0b12011-08-23 11:07:01 +0000187#define CONFIG_BOOTP_PXE
188#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
Matt Waddelb80e41a2010-10-07 15:48:45 -0600189
190/* Miscellaneous configurable options */
191#undef CONFIG_SYS_CLKS_IN_HZ
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000192#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000)
193#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600194#define CONFIG_BOOTDELAY 2
195
Matt Waddelb80e41a2010-10-07 15:48:45 -0600196/* Physical Memory Map */
197#define CONFIG_NR_DRAM_BANKS 2
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000198#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
199#define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + \
200 ((unsigned int)0x20000000))
Matt Waddelb80e41a2010-10-07 15:48:45 -0600201#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
202#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */
203
204/* additions for new relocation code */
205#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk553f0982010-10-26 13:32:32 +0200206#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Matt Waddelb80e41a2010-10-07 15:48:45 -0600207#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200208 CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200209 GENERATED_GBL_DATA_SIZE)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600210#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
211
212/* Basic environment settings */
213#define CONFIG_BOOTCOMMAND "run bootflash;"
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000214#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
215#define CONFIG_PLATFORM_ENV_SETTINGS \
Matt Waddelb80e41a2010-10-07 15:48:45 -0600216 "loadaddr=0x80008000\0" \
Jason Hobbs75e7f3f2011-08-23 11:06:59 +0000217 "ramdisk_addr_r=0x61000000\0" \
218 "kernel_addr=0x44100000\0" \
219 "ramdisk_addr=0x44800000\0" \
220 "maxramdisk=0x1800000\0" \
Jason Hobbse21669f2011-08-23 11:07:00 +0000221 "pxefile_addr_r=0x88000000\0" \
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000222 "kernel_addr_r=0x80008000\0"
223#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
224#define CONFIG_PLATFORM_ENV_SETTINGS \
225 "loadaddr=0xa0008000\0" \
226 "ramdisk_addr_r=0x81000000\0" \
227 "kernel_addr=0x0c100000\0" \
228 "ramdisk_addr=0x0c800000\0" \
229 "maxramdisk=0x1800000\0" \
230 "pxefile_addr_r=0xa8000000\0" \
231 "kernel_addr_r=0xa0008000\0"
232#endif
233#define CONFIG_EXTRA_ENV_SETTINGS \
234 CONFIG_PLATFORM_ENV_SETTINGS \
Matt Waddelb80e41a2010-10-07 15:48:45 -0600235 "console=ttyAMA0,38400n8\0" \
236 "dram=1024M\0" \
237 "root=/dev/sda1 rw\0" \
238 "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
239 "24M@0x2000000(initrd)\0" \
240 "flashargs=setenv bootargs root=${root} console=${console} " \
241 "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
242 "devtmpfs.mount=0 vmalloc=256M\0" \
243 "bootflash=run flashargs; " \
Jason Hobbs75e7f3f2011-08-23 11:06:59 +0000244 "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
245 "bootm ${kernel_addr} ${ramdisk_addr_r}\0"
Matt Waddelb80e41a2010-10-07 15:48:45 -0600246
247/* FLASH and environment organization */
248#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
249#define CONFIG_SYS_FLASH_CFI 1
250#define CONFIG_FLASH_CFI_DRIVER 1
251#define CONFIG_SYS_FLASH_SIZE 0x04000000
252#define CONFIG_SYS_MAX_FLASH_BANKS 2
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000253#define CONFIG_SYS_FLASH_BASE0 V2M_NOR0
254#define CONFIG_SYS_FLASH_BASE1 V2M_NOR1
Matt Waddelb80e41a2010-10-07 15:48:45 -0600255#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0
256
257/* Timeout values in ticks */
258#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
259#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
260
261/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
262#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
263#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
264
265/* Room required on the stack for the environment data */
266#define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE
267
402jagan@gmail.comde1f9ac2012-07-29 04:26:08 +0000268#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
269
Matt Waddelb80e41a2010-10-07 15:48:45 -0600270/*
271 * Amount of flash used for environment:
272 * We don't know which end has the small erase blocks so we use the penultimate
273 * sector location for the environment
274 */
275#define CONFIG_ENV_SECT_SIZE FLASH_MAX_SECTOR_SIZE
276#define CONFIG_ENV_OVERWRITE 1
277
278/* Store environment at top of flash */
279#define CONFIG_ENV_IS_IN_FLASH 1
280#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - \
281 (2 * CONFIG_ENV_SECT_SIZE))
282#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE1 + \
283 CONFIG_ENV_OFFSET)
284#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
285#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
286#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \
287 CONFIG_SYS_FLASH_BASE1 }
288
289/* Monitor Command Prompt */
290#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
291#define CONFIG_SYS_PROMPT "VExpress# "
292#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
293 sizeof(CONFIG_SYS_PROMPT) + 16)
Andre Przywarad21c3af2013-04-09 02:20:33 +0000294#define CONFIG_SYS_HUSH_PARSER
295
Matt Waddelb80e41a2010-10-07 15:48:45 -0600296#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
297#define CONFIG_CMD_SOURCE
298#define CONFIG_SYS_LONGHELP
299#define CONFIG_CMDLINE_EDITING 1
300#define CONFIG_SYS_MAXARGS 16 /* max command args */
301
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000302#endif /* VEXPRESS_COMMON_H */