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Sergey Temerkhanov746f9852015-10-14 09:55:50 -07001/**
2 * (C) Copyright 2014, Cavium Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5**/
6
7#ifndef __THUNDERX_88XX_H__
8#define __THUNDERX_88XX_H__
9
10#define CONFIG_REMAKE_ELF
11
12#define CONFIG_THUNDERX
13
14#define CONFIG_SYS_64BIT
15
16#define CONFIG_SYS_NO_FLASH
17
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070018#define CONFIG_IDENT_STRING \
19 " for Cavium Thunder CN88XX ARM v8 Multi-Core"
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070020
21#define MEM_BASE 0x00500000
22
Sergey Temerkhanov900f88f2015-10-14 09:55:51 -070023#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
24
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070025/* Link Definitions */
26#define CONFIG_SYS_TEXT_BASE 0x00500000
27#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
28
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070029/* SMP Spin Table Definitions */
30#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
31
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070032/* Generic Timer Definitions */
33#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
34
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070035#define CONFIG_SYS_MEMTEST_START MEM_BASE
36#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE)
37
38/* Size of malloc() pool */
39#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
40
41/* PL011 Serial Configuration */
42
43#define CONFIG_PL01X_SERIAL
44#define CONFIG_PL011_CLOCK 24000000
45#define CONFIG_CONS_INDEX 1
46
47/* Generic Interrupt Controller Definitions */
48#define GICD_BASE (0x801000000000)
49#define GICR_BASE (0x801000002000)
50#define CONFIG_SYS_SERIAL0 0x87e024000000
51#define CONFIG_SYS_SERIAL1 0x87e025000000
52
53#define CONFIG_BAUDRATE 115200
54
55/* Command line configuration */
56#define CONFIG_MENU
57
58/* BOOTP options */
59#define CONFIG_BOOTP_BOOTFILESIZE
60#define CONFIG_BOOTP_BOOTPATH
61#define CONFIG_BOOTP_GATEWAY
62#define CONFIG_BOOTP_HOSTNAME
63#define CONFIG_BOOTP_PXE
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070064
65/* Miscellaneous configurable options */
66#define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
67
68/* Physical Memory Map */
69#define CONFIG_NR_DRAM_BANKS 1
70#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
71#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
72#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
73
74/* Initial environment variables */
75#define UBOOT_IMG_HEAD_SIZE 0x40
76/* C80000 - 0x40 */
77#define CONFIG_EXTRA_ENV_SETTINGS \
78 "kernel_addr=08007ffc0\0" \
79 "fdt_addr=0x94C00000\0" \
80 "fdt_high=0x9fffffff\0"
81
82#define CONFIG_BOOTARGS \
83 "console=ttyAMA0,115200n8 " \
84 "earlycon=pl011,0x87e024000000 " \
85 "debug maxcpus=48 rootwait rw "\
86 "root=/dev/sda2 coherent_pool=16M"
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070087
88/* Do not preserve environment */
89#define CONFIG_ENV_IS_NOWHERE 1
90#define CONFIG_ENV_SIZE 0x1000
91
92/* Monitor Command Prompt */
93#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
94#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
95 sizeof(CONFIG_SYS_PROMPT) + 16)
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070096#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
97#define CONFIG_SYS_LONGHELP
98#define CONFIG_CMDLINE_EDITING 1
99#define CONFIG_SYS_MAXARGS 64 /* max command args */
100#define CONFIG_NO_RELOCATION 1
101#define CONFIG_LIB_RAND
102#define PLL_REF_CLK 50000000 /* 50 MHz */
103#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
104
105#endif /* __THUNDERX_88XX_H__ */