blob: 0aad1c2160134e99a9a93d726d981cec696e5509 [file] [log] [blame]
Simon Glass3c5d0e32015-08-30 16:55:33 -06001/*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
Stephen Warren11636252016-05-12 12:03:35 -060010#include <sysreset.h>
Simon Glass3c5d0e32015-08-30 16:55:33 -060011#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/cru_rk3288.h>
14#include <asm/arch/hardware.h>
15#include <linux/err.h>
16
Stephen Warren11636252016-05-12 12:03:35 -060017int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type)
Simon Glass3c5d0e32015-08-30 16:55:33 -060018{
19 struct rk3288_cru *cru = rockchip_get_cru();
20
21 if (IS_ERR(cru))
22 return PTR_ERR(cru);
23 switch (type) {
Stephen Warren11636252016-05-12 12:03:35 -060024 case SYSRESET_WARM:
Simon Glassa49dc0a2016-01-21 19:44:02 -070025 rk_clrreg(&cru->cru_mode_con, 0xffff);
Simon Glass3c5d0e32015-08-30 16:55:33 -060026 writel(0xeca8, &cru->cru_glb_srst_snd_value);
27 break;
Stephen Warren11636252016-05-12 12:03:35 -060028 case SYSRESET_COLD:
Simon Glassa49dc0a2016-01-21 19:44:02 -070029 rk_clrreg(&cru->cru_mode_con, 0xffff);
Simon Glass3c5d0e32015-08-30 16:55:33 -060030 writel(0xfdb9, &cru->cru_glb_srst_fst_value);
31 break;
32 default:
33 return -EPROTONOSUPPORT;
34 }
35
36 return -EINPROGRESS;
37}
38
Stephen Warren11636252016-05-12 12:03:35 -060039static struct sysreset_ops rk3288_sysreset = {
40 .request = rk3288_sysreset_request,
Simon Glass3c5d0e32015-08-30 16:55:33 -060041};
42
Stephen Warren11636252016-05-12 12:03:35 -060043U_BOOT_DRIVER(sysreset_rk3288) = {
44 .name = "rk3288_sysreset",
45 .id = UCLASS_SYSRESET,
46 .ops = &rk3288_sysreset,
Simon Glass3c5d0e32015-08-30 16:55:33 -060047};