jk.kernel@gmail.com | d7ca67b | 2016-07-26 18:28:29 +0800 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2016 Rockchip Electronics Co., Ltd |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ X11 |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "rk3288-fennec.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "Rockchip RK3288 Fennec Board"; |
| 12 | compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; |
| 13 | |
| 14 | chosen { |
| 15 | stdout-path = &uart2; |
| 16 | }; |
| 17 | }; |
| 18 | |
| 19 | &dmc { |
| 20 | rockchip,num-channels = <2>; |
| 21 | rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d |
| 22 | 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 |
| 23 | 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 |
| 24 | 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 |
| 25 | 0x8 0x1f4>; |
| 26 | rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 |
| 27 | 0x0 0xc3 0x6 0x2>; |
| 28 | /* Add a dummy value to cause of-platdata think this is bytes */ |
| 29 | rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 0xff>; |
| 30 | rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; |
| 31 | }; |
| 32 | |
| 33 | &pinctrl { |
| 34 | u-boot,dm-pre-reloc; |
| 35 | }; |
| 36 | |
| 37 | &pwm1 { |
| 38 | status = "okay"; |
| 39 | }; |
| 40 | |
| 41 | &uart2 { |
| 42 | u-boot,dm-pre-reloc; |
| 43 | reg-shift = <2>; |
| 44 | }; |
| 45 | |
| 46 | &sdmmc { |
| 47 | u-boot,dm-pre-reloc; |
| 48 | }; |
| 49 | |
| 50 | &emmc { |
| 51 | u-boot,dm-pre-reloc; |
| 52 | }; |
| 53 | |
| 54 | &gpio3 { |
| 55 | u-boot,dm-pre-reloc; |
| 56 | }; |
| 57 | |
| 58 | &gpio8 { |
| 59 | u-boot,dm-pre-reloc; |
| 60 | }; |