| wdenk | 4a5b6a3 | 2001-04-28 17:59:11 +0000 | [diff] [blame] | 1 | #ifndef __dimm_h |
| 2 | #define __dimm_h |
| 3 | |
| 4 | /* |
| 5 | * Module name: %M% |
| 6 | * Description: |
| 7 | * Serial Presence Detect Definitions Module |
| 8 | * SCCS identification: %I% |
| 9 | * Branch: %B% |
| 10 | * Sequence: %S% |
| 11 | * Date newest applied delta was created (MM/DD/YY): %G% |
| 12 | * Time newest applied delta was created (HH:MM:SS): %U% |
| 13 | * SCCS file name %F% |
| 14 | * Fully qualified SCCS file name: |
| 15 | * %P% |
| 16 | * Copyright: |
| 17 | * (C) COPYRIGHT MOTOROLA, INC. 1996 |
| 18 | * ALL RIGHTS RESERVED |
| 19 | * Notes: |
| 20 | * 1. All data was taken from an IBM application note titled |
| 21 | * "Serial Presence Detect Definitions". |
| 22 | * History: |
| 23 | * Date Who |
| 24 | * |
| 25 | * 10/24/96 Rob Baxter |
| 26 | * Initial release. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | /* |
| 31 | * serial PD byte assignment address map (256 byte EEPROM) |
| 32 | */ |
| 33 | typedef struct dimm |
| 34 | { |
| 35 | uchar n_bytes; /* 00 number of bytes written/used */ |
| 36 | uchar t_bytes; /* 01 total number of bytes in serial PD device */ |
| 37 | uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */ |
| 38 | uchar n_row; /* 03 number of rows */ |
| 39 | uchar n_col; /* 04 number of columns */ |
| 40 | uchar n_banks; /* 05 number of banks */ |
| 41 | uchar data_w_lo; /* 06 data width */ |
| 42 | uchar data_w_hi; /* 07 data width */ |
| 43 | uchar ifl; /* 08 interface levels */ |
| 44 | uchar a_ras; /* 09 RAS access */ |
| 45 | uchar a_cas; /* 0A CAS access */ |
| 46 | uchar ct; /* 0B configuration type (non-parity/parity/ECC) */ |
| 47 | uchar refresh_rt; /* 0C refresh rate/type */ |
| 48 | uchar p_dram_o; /* 0D primary DRAM organization */ |
| 49 | uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */ |
| 50 | uchar reserved[17]; /* 0F reserved fields for future offerings */ |
| 51 | uchar ss_info[32]; /* 20 superset information (may be used in the future) */ |
| 52 | uchar m_info[64]; /* 40 manufacturer information (optional) */ |
| 53 | uchar unused[128]; /* 80 unused storage locations */ |
| 54 | } dimm_t; |
| 55 | |
| 56 | /* |
| 57 | * memory type definitions |
| 58 | */ |
| 59 | #define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */ |
| 60 | #define DIMM_MT_EDO 2 /* EDO (extended data out) */ |
| 61 | #define DIMM_MT_PN 3 /* pipelined nibble */ |
| 62 | #define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */ |
| 63 | |
| 64 | /* |
| 65 | * row addresses definitions |
| 66 | */ |
| 67 | #define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */ |
| 68 | #define DIMM_RA_MASK 0x7f /* number of row addresses mask */ |
| 69 | |
| 70 | /* |
| 71 | * module interface levels definitions |
| 72 | */ |
| 73 | #define DIMM_IFL_TTL 0 /* TTL/5V tolerant */ |
| 74 | #define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */ |
| 75 | #define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */ |
| 76 | #define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */ |
| 77 | #define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */ |
| 78 | |
| 79 | /* |
| 80 | * DIMM configuration type definitions |
| 81 | */ |
| 82 | #define DIMM_CT_NONE 0 /* none */ |
| 83 | #define DIMM_CT_PARITY 1 /* parity */ |
| 84 | #define DIMM_CT_ECC 2 /* ECC */ |
| 85 | |
| 86 | /* |
| 87 | * row addresses definitions |
| 88 | */ |
| 89 | #define DIMM_RRT_SR (1<<7) /* self refresh flag */ |
| 90 | #define DIMM_RRT_MASK 0x7f /* refresh rate mask */ |
| 91 | #define DIMM_RRT_NRML 0x00 /* normal (15.625us) */ |
| 92 | #define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */ |
| 93 | #define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */ |
| 94 | #define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */ |
| 95 | #define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */ |
| 96 | #define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */ |
| 97 | |
| 98 | #endif /* __dimm_h */ |