| Mike Frysinger | d9a5d11 | 2008-10-12 20:59:12 -0400 | [diff] [blame] | 1 | /* |
| 2 | * U-boot - u-boot.lds.S |
| 3 | * |
| 4 | * Copyright (c) 2005-2008 Analog Device Inc. |
| 5 | * |
| 6 | * (C) Copyright 2000-2004 |
| 7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | #include <config.h> |
| 29 | #include <asm/blackfin.h> |
| 30 | #undef ALIGN |
| 31 | #undef ENTRY |
| 32 | #undef bfin |
| 33 | |
| 34 | /* If we don't actually load anything into L1 data, this will avoid |
| 35 | * a syntax error. If we do actually load something into L1 data, |
| 36 | * we'll get a linker memory load error (which is what we'd want). |
| 37 | * This is here in the first place so we can quickly test building |
| 38 | * for different CPU's which may lack non-cache L1 data. |
| 39 | */ |
| 40 | #ifndef L1_DATA_B_SRAM |
| 41 | # define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE |
| 42 | # define L1_DATA_B_SRAM_SIZE 0 |
| 43 | #endif |
| 44 | |
| 45 | OUTPUT_ARCH(bfin) |
| 46 | |
| 47 | MEMORY |
| 48 | { |
| 49 | ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN |
| 50 | l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE |
| 51 | l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE |
| 52 | } |
| 53 | |
| 54 | ENTRY(_start) |
| 55 | SECTIONS |
| 56 | { |
| 57 | .text : |
| 58 | { |
| 59 | cpu/blackfin/start.o (.text .text.*) |
| 60 | __initcode_start = .; |
| 61 | cpu/blackfin/initcode.o (.text .text.*) |
| 62 | __initcode_end = .; |
| 63 | *(.text .text.*) |
| 64 | } >ram |
| 65 | |
| 66 | .rodata : |
| 67 | { |
| 68 | . = ALIGN(4); |
| 69 | *(.rodata .rodata.*) |
| 70 | *(.rodata1) |
| 71 | *(.eh_frame) |
| 72 | . = ALIGN(4); |
| 73 | } >ram |
| 74 | |
| 75 | .data : |
| 76 | { |
| 77 | . = ALIGN(256); |
| 78 | *(.data .data.*) |
| 79 | *(.data1) |
| 80 | *(.sdata) |
| 81 | *(.sdata2) |
| 82 | *(.dynamic) |
| 83 | CONSTRUCTORS |
| 84 | } >ram |
| 85 | |
| 86 | .u_boot_cmd : |
| 87 | { |
| 88 | ___u_boot_cmd_start = .; |
| 89 | *(.u_boot_cmd) |
| 90 | ___u_boot_cmd_end = .; |
| 91 | } >ram |
| 92 | |
| 93 | .text_l1 : |
| 94 | { |
| 95 | . = ALIGN(4); |
| 96 | __stext_l1 = .; |
| 97 | *(.l1.text) |
| 98 | . = ALIGN(4); |
| 99 | __etext_l1 = .; |
| 100 | } >l1_code AT>ram |
| 101 | __stext_l1_lma = LOADADDR(.text_l1); |
| 102 | |
| 103 | .data_l1 : |
| 104 | { |
| 105 | . = ALIGN(4); |
| 106 | __sdata_l1 = .; |
| 107 | *(.l1.data) |
| 108 | *(.l1.bss) |
| 109 | . = ALIGN(4); |
| 110 | __edata_l1 = .; |
| 111 | } >l1_data AT>ram |
| 112 | __sdata_l1_lma = LOADADDR(.data_l1); |
| 113 | |
| 114 | .bss : |
| 115 | { |
| 116 | . = ALIGN(4); |
| 117 | __bss_start = .; |
| 118 | *(.sbss) *(.scommon) |
| 119 | *(.dynbss) |
| 120 | *(.bss .bss.*) |
| 121 | *(COMMON) |
| 122 | __bss_end = .; |
| 123 | } >ram |
| 124 | } |