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Jaehoon Chungd0ebbb82012-10-15 19:10:31 +00001/*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +00006 */
7
8#include <common.h>
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +00009#include <dwmmc.h>
Amara082a2d2013-04-27 11:42:55 +053010#include <fdtdec.h>
11#include <libfdt.h>
12#include <malloc.h>
Jaehoon Chungccd60a82016-07-19 16:33:34 +090013#include <errno.h>
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000014#include <asm/arch/dwmmc.h>
15#include <asm/arch/clk.h>
Amara082a2d2013-04-27 11:42:55 +053016#include <asm/arch/pinmux.h>
Przemyslaw Marczak64029f72015-02-20 12:29:26 +010017#include <asm/arch/power.h>
Jaehoon Chung959198f2014-05-16 13:59:52 +090018#include <asm/gpio.h>
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000019
Amara082a2d2013-04-27 11:42:55 +053020#define DWMMC_MAX_CH_NUM 4
21#define DWMMC_MAX_FREQ 52000000
22#define DWMMC_MIN_FREQ 400000
Jaehoon Chung5dab81c2015-02-04 15:48:40 +090023#define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001
24#define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001
25
Jaehoon Chung3537ee82016-06-30 20:57:37 +090026#ifdef CONFIG_DM_MMC
27#include <dm.h>
28DECLARE_GLOBAL_DATA_PTR;
29
30struct exynos_mmc_plat {
31 struct mmc_config cfg;
32 struct mmc mmc;
33};
34#endif
35
Jaehoon Chung5dab81c2015-02-04 15:48:40 +090036/* Exynos implmentation specific drver private data */
37struct dwmci_exynos_priv_data {
Jaehoon Chung3537ee82016-06-30 20:57:37 +090038#ifdef CONFIG_DM_MMC
39 struct dwmci_host host;
40#endif
Jaehoon Chung5dab81c2015-02-04 15:48:40 +090041 u32 sdr_timing;
42};
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000043
Amara082a2d2013-04-27 11:42:55 +053044/*
45 * Function used as callback function to initialise the
46 * CLKSEL register for every mmc channel.
47 */
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000048static void exynos_dwmci_clksel(struct dwmci_host *host)
49{
Jaehoon Chung5dab81c2015-02-04 15:48:40 +090050 struct dwmci_exynos_priv_data *priv = host->priv;
51
52 dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000053}
54
Simon Glasse3563f22015-08-30 16:55:15 -060055unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
Amara082a2d2013-04-27 11:42:55 +053056{
Rajeshwari S Shinded3e016c2014-02-05 10:48:15 +053057 unsigned long sclk;
58 int8_t clk_div;
59
60 /*
61 * Since SDCLKIN is divided inside controller by the DIVRATIO
62 * value set in the CLKSEL register, we need to use the same output
63 * clock value to calculate the CLKDIV value.
64 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
65 */
66 clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
67 & DWMCI_DIVRATIO_MASK) + 1;
68 sclk = get_mmc_clk(host->dev_index);
69
Jaehoon Chung959198f2014-05-16 13:59:52 +090070 /*
71 * Assume to know divider value.
72 * When clock unit is broken, need to set "host->div"
73 */
74 return sclk / clk_div / (host->div + 1);
Amara082a2d2013-04-27 11:42:55 +053075}
76
Jaehoon Chung18ab6752013-11-29 20:08:57 +090077static void exynos_dwmci_board_init(struct dwmci_host *host)
78{
Jaehoon Chung5dab81c2015-02-04 15:48:40 +090079 struct dwmci_exynos_priv_data *priv = host->priv;
80
Jaehoon Chung18ab6752013-11-29 20:08:57 +090081 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
82 dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
83 dwmci_writel(host, EMMCP_SEND0, 0);
84 dwmci_writel(host, EMMCP_CTRL0,
85 MPSCTRL_SECURE_READ_BIT |
86 MPSCTRL_SECURE_WRITE_BIT |
87 MPSCTRL_NON_SECURE_READ_BIT |
88 MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
89 }
Jaehoon Chung3a33bb12015-02-04 15:48:39 +090090
Jaehoon Chung5dab81c2015-02-04 15:48:40 +090091 /* Set to timing value at initial time */
92 if (priv->sdr_timing)
Jaehoon Chung3a33bb12015-02-04 15:48:39 +090093 exynos_dwmci_clksel(host);
Jaehoon Chung18ab6752013-11-29 20:08:57 +090094}
95
Jaehoon Chungd956a672016-06-29 19:46:17 +090096static int exynos_dwmci_core_init(struct dwmci_host *host)
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000097{
Amara082a2d2013-04-27 11:42:55 +053098 unsigned int div;
99 unsigned long freq, sclk;
Jaehoon Chung959198f2014-05-16 13:59:52 +0900100
101 if (host->bus_hz)
102 freq = host->bus_hz;
103 else
104 freq = DWMMC_MAX_FREQ;
105
Amara082a2d2013-04-27 11:42:55 +0530106 /* request mmc clock vlaue of 52MHz. */
Jaehoon Chungd956a672016-06-29 19:46:17 +0900107 sclk = get_mmc_clk(host->dev_index);
Amara082a2d2013-04-27 11:42:55 +0530108 div = DIV_ROUND_UP(sclk, freq);
109 /* set the clock divisor for mmc */
Jaehoon Chungd956a672016-06-29 19:46:17 +0900110 set_mmc_clk(host->dev_index, div);
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +0000111
Amara082a2d2013-04-27 11:42:55 +0530112 host->name = "EXYNOS DWMMC";
Rajeshwari Shinde6f0b7ca2013-10-29 12:53:13 +0530113#ifdef CONFIG_EXYNOS5420
114 host->quirks = DWMCI_QUIRK_DISABLE_SMU;
115#endif
Jaehoon Chung18ab6752013-11-29 20:08:57 +0900116 host->board_init = exynos_dwmci_board_init;
Amara082a2d2013-04-27 11:42:55 +0530117
Jaehoon Chunge09bd852014-05-16 13:59:57 +0900118 host->caps = MMC_MODE_DDR_52MHz;
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +0000119 host->clksel = exynos_dwmci_clksel;
Jaehoon Chungb44fe832013-10-06 18:59:31 +0900120 host->get_mmc_clk = exynos_dwmci_get_clk;
Jaehoon Chung3537ee82016-06-30 20:57:37 +0900121
122#ifndef CONFIG_DM_MMC
Amara082a2d2013-04-27 11:42:55 +0530123 /* Add the mmc channel to be registered with mmc core */
124 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
Jaehoon Chungd956a672016-06-29 19:46:17 +0900125 printf("DWMMC%d registration failed\n", host->dev_index);
Amara082a2d2013-04-27 11:42:55 +0530126 return -1;
127 }
Jaehoon Chung3537ee82016-06-30 20:57:37 +0900128#endif
129
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +0000130 return 0;
131}
132
Jaehoon Chung959198f2014-05-16 13:59:52 +0900133static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
134
135static int do_dwmci_init(struct dwmci_host *host)
136{
Jaehoon Chungd956a672016-06-29 19:46:17 +0900137 int flag, err;
Jaehoon Chung959198f2014-05-16 13:59:52 +0900138
139 flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
140 err = exynos_pinmux_config(host->dev_id, flag);
141 if (err) {
Jaehoon Chungd956a672016-06-29 19:46:17 +0900142 printf("DWMMC%d not configure\n", host->dev_index);
Jaehoon Chung959198f2014-05-16 13:59:52 +0900143 return err;
144 }
145
Jaehoon Chungd956a672016-06-29 19:46:17 +0900146 return exynos_dwmci_core_init(host);
Jaehoon Chung959198f2014-05-16 13:59:52 +0900147}
148
149static int exynos_dwmci_get_config(const void *blob, int node,
150 struct dwmci_host *host)
151{
152 int err = 0;
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900153 u32 base, timing[3];
154 struct dwmci_exynos_priv_data *priv;
155
156 priv = malloc(sizeof(struct dwmci_exynos_priv_data));
157 if (!priv) {
158 error("dwmci_exynos_priv_data malloc fail!\n");
159 return -ENOMEM;
160 }
Jaehoon Chung959198f2014-05-16 13:59:52 +0900161
162 /* Extract device id for each mmc channel */
163 host->dev_id = pinmux_decode_periph_id(blob, node);
164
Jaehoon Chung959198f2014-05-16 13:59:52 +0900165 host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
166 if (host->dev_index == host->dev_id)
167 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
168
Jaehoon Chungce757b12016-06-29 19:46:16 +0900169 if (host->dev_index > 4) {
170 printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
171 return -EINVAL;
172 }
173
Jaehoon Chung70f6d392016-06-29 19:46:18 +0900174 /* Get the bus width from the device node (Default is 4bit buswidth) */
175 host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);
Jaehoon Chungdfcb6832014-11-28 20:42:33 +0900176
Jaehoon Chung959198f2014-05-16 13:59:52 +0900177 /* Set the base address from the device node */
178 base = fdtdec_get_addr(blob, node, "reg");
179 if (!base) {
Jaehoon Chungdfcb6832014-11-28 20:42:33 +0900180 printf("DWMMC%d: Can't get base address\n", host->dev_index);
Jaehoon Chung959198f2014-05-16 13:59:52 +0900181 return -EINVAL;
182 }
183 host->ioaddr = (void *)base;
184
185 /* Extract the timing info from the node */
186 err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
187 if (err) {
Jaehoon Chungdfcb6832014-11-28 20:42:33 +0900188 printf("DWMMC%d: Can't get sdr-timings for devider\n",
189 host->dev_index);
Jaehoon Chung959198f2014-05-16 13:59:52 +0900190 return -EINVAL;
191 }
192
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900193 priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
Jaehoon Chung959198f2014-05-16 13:59:52 +0900194 DWMCI_SET_DRV_CLK(timing[1]) |
195 DWMCI_SET_DIV_RATIO(timing[2]));
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900196
197 /* sdr_timing didn't assigned anything, use the default value */
198 if (!priv->sdr_timing) {
199 if (host->dev_index == 0)
200 priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
201 else if (host->dev_index == 2)
202 priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
203 }
Jaehoon Chung959198f2014-05-16 13:59:52 +0900204
205 host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
206 host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
207 host->div = fdtdec_get_int(blob, node, "div", 0);
208
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900209 host->priv = priv;
210
Jaehoon Chung959198f2014-05-16 13:59:52 +0900211 return 0;
212}
213
214static int exynos_dwmci_process_node(const void *blob,
215 int node_list[], int count)
216{
217 struct dwmci_host *host;
218 int i, node, err;
Amara082a2d2013-04-27 11:42:55 +0530219
220 for (i = 0; i < count; i++) {
Jaehoon Chung959198f2014-05-16 13:59:52 +0900221 node = node_list[i];
Amara082a2d2013-04-27 11:42:55 +0530222 if (node <= 0)
223 continue;
Jaehoon Chung959198f2014-05-16 13:59:52 +0900224 host = &dwmci_host[i];
225 err = exynos_dwmci_get_config(blob, node, host);
Amara082a2d2013-04-27 11:42:55 +0530226 if (err) {
Jaehoon Chungdfcb6832014-11-28 20:42:33 +0900227 printf("%s: failed to decode dev %d\n", __func__, i);
Amara082a2d2013-04-27 11:42:55 +0530228 return err;
229 }
230
Jaehoon Chung959198f2014-05-16 13:59:52 +0900231 do_dwmci_init(host);
Amara082a2d2013-04-27 11:42:55 +0530232 }
233 return 0;
234}
Jaehoon Chung959198f2014-05-16 13:59:52 +0900235
236int exynos_dwmmc_init(const void *blob)
237{
Jaehoon Chung959198f2014-05-16 13:59:52 +0900238 int node_list[DWMMC_MAX_CH_NUM];
Przemyslaw Marczak64029f72015-02-20 12:29:26 +0100239 int boot_dev_node;
Jaehoon Chung959198f2014-05-16 13:59:52 +0900240 int err = 0, count;
241
Jaehoon Chung959198f2014-05-16 13:59:52 +0900242 count = fdtdec_find_aliases_for_id(blob, "mmc",
Jaehoon Chungd956a672016-06-29 19:46:17 +0900243 COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list,
244 DWMMC_MAX_CH_NUM);
Przemyslaw Marczak64029f72015-02-20 12:29:26 +0100245
246 /* For DWMMC always set boot device as mmc 0 */
247 if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) {
248 boot_dev_node = node_list[2];
249 node_list[2] = node_list[0];
250 node_list[0] = boot_dev_node;
251 }
252
Jaehoon Chung959198f2014-05-16 13:59:52 +0900253 err = exynos_dwmci_process_node(blob, node_list, count);
254
255 return err;
256}
Jaehoon Chung3537ee82016-06-30 20:57:37 +0900257
258#ifdef CONFIG_DM_MMC
259static int exynos_dwmmc_probe(struct udevice *dev)
260{
261 struct exynos_mmc_plat *plat = dev_get_platdata(dev);
262 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
263 struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
264 struct dwmci_host *host = &priv->host;
265 int err;
266
267 err = exynos_dwmci_get_config(gd->fdt_blob, dev->of_offset, host);
268 if (err)
269 return err;
270 err = do_dwmci_init(host);
271 if (err)
272 return err;
273
274 dwmci_setup_cfg(&plat->cfg, host->name, host->buswidth, host->caps,
275 DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
276 host->mmc = &plat->mmc;
277 host->mmc->priv = &priv->host;
278 host->priv = dev;
279 upriv->mmc = host->mmc;
280
281 return dwmci_probe(dev);
282}
283
284static int exynos_dwmmc_bind(struct udevice *dev)
285{
286 struct exynos_mmc_plat *plat = dev_get_platdata(dev);
Jaehoon Chung3537ee82016-06-30 20:57:37 +0900287
Masahiro Yamada24f5aec2016-09-06 22:17:32 +0900288 return dwmci_bind(dev, &plat->mmc, &plat->cfg);
Jaehoon Chung3537ee82016-06-30 20:57:37 +0900289}
290
291static const struct udevice_id exynos_dwmmc_ids[] = {
292 { .compatible = "samsung,exynos4412-dw-mshc" },
293 { }
294};
295
296U_BOOT_DRIVER(exynos_dwmmc_drv) = {
297 .name = "exynos_dwmmc",
298 .id = UCLASS_MMC,
299 .of_match = exynos_dwmmc_ids,
300 .bind = exynos_dwmmc_bind,
301 .ops = &dm_dwmci_ops,
302 .probe = exynos_dwmmc_probe,
303 .priv_auto_alloc_size = sizeof(struct dwmci_exynos_priv_data),
304 .platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat),
305};
306#endif