Shaohui Xie | 02b5d2e | 2015-11-11 17:58:37 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2015 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <fsl_ddr_sdram.h> |
| 9 | #include <fsl_ddr_dimm_params.h> |
| 10 | #ifdef CONFIG_FSL_DEEP_SLEEP |
| 11 | #include <fsl_sleep.h> |
| 12 | #endif |
| 13 | #include "ddr.h" |
| 14 | |
| 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
| 17 | void fsl_ddr_board_options(memctl_options_t *popts, |
| 18 | dimm_params_t *pdimm, |
| 19 | unsigned int ctrl_num) |
| 20 | { |
| 21 | const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
| 22 | ulong ddr_freq; |
| 23 | |
| 24 | if (ctrl_num > 3) { |
| 25 | printf("Not supported controller number %d\n", ctrl_num); |
| 26 | return; |
| 27 | } |
| 28 | if (!pdimm->n_ranks) |
| 29 | return; |
| 30 | |
| 31 | pbsp = udimms[0]; |
| 32 | |
| 33 | /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr |
| 34 | * freqency and n_banks specified in board_specific_parameters table. |
| 35 | */ |
| 36 | ddr_freq = get_ddr_freq(0) / 1000000; |
| 37 | while (pbsp->datarate_mhz_high) { |
| 38 | if (pbsp->n_ranks == pdimm->n_ranks) { |
| 39 | if (ddr_freq <= pbsp->datarate_mhz_high) { |
| 40 | popts->clk_adjust = pbsp->clk_adjust; |
| 41 | popts->wrlvl_start = pbsp->wrlvl_start; |
| 42 | popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
| 43 | popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
| 44 | popts->cpo_override = pbsp->cpo_override; |
| 45 | popts->write_data_delay = |
| 46 | pbsp->write_data_delay; |
| 47 | goto found; |
| 48 | } |
| 49 | pbsp_highest = pbsp; |
| 50 | } |
| 51 | pbsp++; |
| 52 | } |
| 53 | |
| 54 | if (pbsp_highest) { |
| 55 | printf("Error: board specific timing not found for %lu MT/s\n", |
| 56 | ddr_freq); |
| 57 | printf("Trying to use the highest speed (%u) parameters\n", |
| 58 | pbsp_highest->datarate_mhz_high); |
| 59 | popts->clk_adjust = pbsp_highest->clk_adjust; |
| 60 | popts->wrlvl_start = pbsp_highest->wrlvl_start; |
| 61 | popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
| 62 | popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
| 63 | } else { |
| 64 | panic("DIMM is not supported by this board"); |
| 65 | } |
| 66 | found: |
| 67 | debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", |
| 68 | pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); |
| 69 | |
| 70 | /* force DDR bus width to 32 bits */ |
| 71 | popts->data_bus_width = 1; |
| 72 | popts->otf_burst_chop_en = 0; |
| 73 | popts->burst_length = DDR_BL8; |
| 74 | popts->bstopre = 0; /* enable auto precharge */ |
| 75 | |
| 76 | /* |
| 77 | * Factors to consider for half-strength driver enable: |
| 78 | * - number of DIMMs installed |
| 79 | */ |
| 80 | popts->half_strength_driver_enable = 1; |
| 81 | /* |
| 82 | * Write leveling override |
| 83 | */ |
| 84 | popts->wrlvl_override = 1; |
| 85 | popts->wrlvl_sample = 0xf; |
| 86 | |
| 87 | /* |
| 88 | * Rtt and Rtt_WR override |
| 89 | */ |
| 90 | popts->rtt_override = 0; |
| 91 | |
| 92 | /* Enable ZQ calibration */ |
| 93 | popts->zq_en = 1; |
| 94 | |
| 95 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 96 | popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); |
| 97 | popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | |
| 98 | DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ |
| 99 | #else |
| 100 | popts->cswl_override = DDR_CSWL_CS0; |
| 101 | |
| 102 | /* DHC_EN =1, ODT = 75 Ohm */ |
| 103 | popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); |
| 104 | popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); |
| 105 | #endif |
| 106 | } |
| 107 | |
| 108 | phys_size_t initdram(int board_type) |
| 109 | { |
| 110 | phys_size_t dram_size; |
| 111 | |
| 112 | #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) |
| 113 | return fsl_ddr_sdram_size(); |
| 114 | #else |
| 115 | puts("Initializing DDR....using SPD\n"); |
| 116 | |
| 117 | dram_size = fsl_ddr_sdram(); |
| 118 | #endif |
| 119 | |
| 120 | #ifdef CONFIG_FSL_DEEP_SLEEP |
| 121 | fsl_dp_ddr_restore(); |
| 122 | #endif |
| 123 | |
| 124 | return dram_size; |
| 125 | } |
| 126 | |
| 127 | void dram_init_banksize(void) |
| 128 | { |
York Sun | c107c0c | 2015-12-04 11:57:08 -0800 | [diff] [blame] | 129 | /* |
| 130 | * gd->secure_ram tracks the location of secure memory. |
| 131 | * It was set as if the memory starts from 0. |
| 132 | * The address needs to add the offset of its bank. |
| 133 | */ |
Shaohui Xie | 02b5d2e | 2015-11-11 17:58:37 +0800 | [diff] [blame] | 134 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
Shaohui Xie | 58e4ad1 | 2016-01-04 11:03:44 +0800 | [diff] [blame] | 135 | if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { |
| 136 | gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; |
| 137 | gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; |
| 138 | gd->bd->bi_dram[1].size = gd->ram_size - |
| 139 | CONFIG_SYS_DDR_BLOCK1_SIZE; |
York Sun | c107c0c | 2015-12-04 11:57:08 -0800 | [diff] [blame] | 140 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
Shaohui Xie | 58e4ad1 | 2016-01-04 11:03:44 +0800 | [diff] [blame] | 141 | gd->secure_ram = gd->bd->bi_dram[1].start + |
| 142 | gd->secure_ram - |
| 143 | CONFIG_SYS_DDR_BLOCK1_SIZE; |
| 144 | gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; |
York Sun | c107c0c | 2015-12-04 11:57:08 -0800 | [diff] [blame] | 145 | #endif |
Shaohui Xie | 58e4ad1 | 2016-01-04 11:03:44 +0800 | [diff] [blame] | 146 | } else { |
| 147 | gd->bd->bi_dram[0].size = gd->ram_size; |
| 148 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
| 149 | gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; |
| 150 | gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; |
| 151 | #endif |
| 152 | } |
Shaohui Xie | 02b5d2e | 2015-11-11 17:58:37 +0800 | [diff] [blame] | 153 | } |