| Bhupesh Sharma | 3ffa95c | 2015-07-01 09:58:03 +0530 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2015 Freescale Semiconductor |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | * |
| 6 | * Extracted from gic_64.S |
| 7 | */ |
| 8 | |
| 9 | #include <config.h> |
| 10 | #include <linux/linkage.h> |
| 11 | #include <asm/macro.h> |
| 12 | |
| 13 | /************************************************************************* |
| 14 | * |
| 15 | * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST, |
| 16 | * CCI_MN_DVM_DOMAIN_CTL_SET); |
| 17 | * |
| 18 | * Add fully-coherent masters to DVM domain |
| 19 | * |
| 20 | *************************************************************************/ |
| 21 | ENTRY(ccn504_add_masters_to_dvm) |
| 22 | /* |
| 23 | * x0: CCI_MN_BASE |
| 24 | * x1: CCI_MN_RNF_NODEID_LIST |
| 25 | * x2: CCI_MN_DVM_DOMAIN_CTL_SET |
| 26 | */ |
| 27 | |
| 28 | /* Add fully-coherent masters to DVM domain */ |
| 29 | ldr x9, [x0, x1] |
| 30 | str x9, [x0, x2] |
| 31 | 1: ldr x10, [x0, x2] |
| 32 | mvn x11, x10 |
| 33 | tst x11, x10 /* Wait for domain addition to complete */ |
| 34 | b.ne 1b |
| 35 | |
| 36 | ret |
| 37 | ENDPROC(ccn504_add_masters_to_dvm) |
| 38 | |
| 39 | /************************************************************************* |
| 40 | * |
| 41 | * void ccn504_set_qos(CCI_Sx_QOS_CONTROL_BASE, QoS Value); |
| 42 | * |
| 43 | * Initialize QoS settings for AR/AW override. |
| 44 | * Right now, this function sets the same QoS value for all RN-I ports |
| 45 | * |
| 46 | *************************************************************************/ |
| 47 | ENTRY(ccn504_set_qos) |
| 48 | /* |
| 49 | * x0: CCI_Sx_QOS_CONTROL_BASE |
| 50 | * x1: QoS Value |
| 51 | */ |
| 52 | |
| 53 | /* Set all RN-I ports to QoS value denoted by x1 */ |
| 54 | ldr x9, [x0] |
| 55 | mov x10, x1 |
| 56 | orr x9, x9, x10 |
| 57 | str x9, [x0] |
| 58 | |
| 59 | ret |
| 60 | ENDPROC(ccn504_set_qos) |
| 61 | |