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Masahiro Yamada5894ca02014-10-03 19:21:06 +09001/*
2 * Copyright (C) 2012-2014 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8/* U-boot - Common settings for UniPhier Family */
9
10#ifndef __CONFIG_UNIPHIER_COMMON_H__
11#define __CONFIG_UNIPHIER_COMMON_H__
12
Masahiro Yamadaf5d0b9b2014-12-06 00:03:22 +090013#if defined(CONFIG_MACH_PH1_PRO4)
14#define CONFIG_DDR_NUM_CH0 2
15#define CONFIG_DDR_NUM_CH1 2
16
17/* Physical start address of SDRAM */
18#define CONFIG_SDRAM0_BASE 0x80000000
19#define CONFIG_SDRAM0_SIZE 0x20000000
20#define CONFIG_SDRAM1_BASE 0xa0000000
21#define CONFIG_SDRAM1_SIZE 0x20000000
22#endif
23
24#if defined(CONFIG_MACH_PH1_LD4)
25#define CONFIG_DDR_NUM_CH0 1
26#define CONFIG_DDR_NUM_CH1 1
27
28/* Physical start address of SDRAM */
29#define CONFIG_SDRAM0_BASE 0x80000000
30#define CONFIG_SDRAM0_SIZE 0x10000000
31#define CONFIG_SDRAM1_BASE 0x90000000
32#define CONFIG_SDRAM1_SIZE 0x10000000
33#endif
34
35#if defined(CONFIG_MACH_PH1_SLD8)
36#define CONFIG_DDR_NUM_CH0 1
37#define CONFIG_DDR_NUM_CH1 1
38
39/* Physical start address of SDRAM */
40#define CONFIG_SDRAM0_BASE 0x80000000
41#define CONFIG_SDRAM0_SIZE 0x10000000
42#define CONFIG_SDRAM1_BASE 0x90000000
43#define CONFIG_SDRAM1_SIZE 0x10000000
44#endif
45
Masahiro Yamada233e42a2015-01-13 12:44:39 +090046#define CONFIG_I2C_EEPROM
47#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
48
Masahiro Yamada5894ca02014-10-03 19:21:06 +090049/*
50 * Support card address map
51 */
52#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
53# define CONFIG_SUPPORT_CARD_BASE 0x03f00000
54# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
55# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
56# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
57#endif
58
59#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
60# define CONFIG_SUPPORT_CARD_BASE 0x08000000
61# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
62# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
63# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
64#endif
65
Masahiro Yamadad064cbf2014-10-23 22:26:10 +090066#ifdef CONFIG_SYS_NS16550_SERIAL
Masahiro Yamada5894ca02014-10-03 19:21:06 +090067#define CONFIG_SYS_NS16550
68#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
69#define CONFIG_SYS_NS16550_CLK 12288000
70#define CONFIG_SYS_NS16550_REG_SIZE -2
Masahiro Yamadad064cbf2014-10-23 22:26:10 +090071#endif
Masahiro Yamada5894ca02014-10-03 19:21:06 +090072
Masahiro Yamadaf5d0b9b2014-12-06 00:03:22 +090073/* TODO: move to Kconfig and device tree */
74#if 0
75#define CONFIG_SYS_NS16550_SERIAL
76#endif
77
78#define CONFIG_SMC911X
79
Masahiro Yamada5894ca02014-10-03 19:21:06 +090080#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
81#define CONFIG_SMC911X_32_BIT
82
Masahiro Yamada0d8c7f72014-11-11 21:50:41 +090083#define CONFIG_SYS_MALLOC_F_LEN 0x2000
Masahiro Yamada5894ca02014-10-03 19:21:06 +090084
85/*-----------------------------------------------------------------------
86 * MMU and Cache Setting
87 *----------------------------------------------------------------------*/
88
89/* Comment out the following to enable L1 cache */
90/* #define CONFIG_SYS_ICACHE_OFF */
91/* #define CONFIG_SYS_DCACHE_OFF */
92
93/* Comment out the following to enable L2 cache */
94#define CONFIG_UNIPHIER_L2CACHE_ON
95
96#define CONFIG_DISPLAY_CPUINFO
97#define CONFIG_DISPLAY_BOARDINFO
Masahiro Yamada7a3620b2014-12-06 00:03:26 +090098#define CONFIG_BOARD_EARLY_INIT_R
Masahiro Yamada5894ca02014-10-03 19:21:06 +090099#define CONFIG_BOARD_LATE_INIT
100
101#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
102
103#define CONFIG_TIMESTAMP
104
105/* FLASH related */
106#define CONFIG_MTD_DEVICE
107
108/*
109 * uncomment the following to disable FLASH related code.
110 */
111/* #define CONFIG_SYS_NO_FLASH */
112
113#define CONFIG_FLASH_CFI_DRIVER
114#define CONFIG_SYS_FLASH_CFI
115
116#define CONFIG_SYS_MAX_FLASH_SECT 256
117#define CONFIG_SYS_MONITOR_BASE 0
118#define CONFIG_SYS_FLASH_BASE 0
119
120/*
121 * flash_toggle does not work for out supoort card.
122 * We need to use flash_status_poll.
123 */
124#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
125
126#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
127
Masahiro Yamada7a3620b2014-12-06 00:03:26 +0900128#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900129
130/* serial console configuration */
131#define CONFIG_BAUDRATE 115200
132
133#define CONFIG_SYS_GENERIC_BOARD
134
135#if !defined(CONFIG_SPL_BUILD)
136#define CONFIG_USE_ARCH_MEMSET
137#define CONFIG_USE_ARCH_MEMCPY
138#endif
139
140#define CONFIG_SYS_LONGHELP /* undef to save memory */
141
142#define CONFIG_CMDLINE_EDITING /* add command line history */
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900143#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
144/* Print Buffer Size */
145#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
146#define CONFIG_SYS_MAXARGS 16 /* max number of command */
147/* Boot Argument Buffer Size */
148#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
149
150#define CONFIG_CONS_INDEX 1
151
152/*
153 * For NAND booting the environment is embedded in the U-Boot image. Please take
154 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
155 */
156/* #define CONFIG_ENV_IS_IN_NAND */
157#define CONFIG_ENV_IS_NOWHERE
158#define CONFIG_ENV_SIZE 0x2000
159#define CONFIG_ENV_OFFSET 0x0
160/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
161
162/* Time clock 1MHz */
163#define CONFIG_SYS_TIMER_RATE 1000000
164
165/*
166 * By default, ARP timeout is 5 sec.
167 * The first ARP request does not seem to work.
168 * So we need to retry ARP request anyway.
169 * We want to shrink the interval until the second ARP request.
170 */
171#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
172
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900173#define CONFIG_SYS_MAX_NAND_DEVICE 1
174#define CONFIG_SYS_NAND_MAX_CHIPS 2
175#define CONFIG_SYS_NAND_ONFI_DETECTION
176
177#define CONFIG_NAND_DENALI_ECC_SIZE 1024
178
179#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
180#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
181
182#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
183
184#define CONFIG_SYS_NAND_USE_FLASH_BBT
185#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
186
Masahiro Yamada495deb42014-11-07 18:48:34 +0900187/* USB */
Masahiro Yamada495deb42014-11-07 18:48:34 +0900188#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
189#define CONFIG_CMD_FAT
190#define CONFIG_FAT_WRITE
191#define CONFIG_DOS_PARTITION
192
Masahiro Yamadad8bec602014-12-18 19:11:04 +0900193#define CONFIG_CMD_DM
194
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900195/* memtest works on */
196#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
197#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
198
199#define CONFIG_BOOTDELAY 3
200#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
201#define CONFIG_AUTOBOOT_KEYED 1
202#define CONFIG_AUTOBOOT_PROMPT \
203 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
204#define CONFIG_AUTOBOOT_DELAY_STR "d"
205#define CONFIG_AUTOBOOT_STOP_STR " "
206
207/*
208 * Network Configuration
209 */
210#define CONFIG_ETHADDR 00:21:83:24:00:00
211#define CONFIG_SERVERIP 192.168.11.1
212#define CONFIG_IPADDR 192.168.11.10
213#define CONFIG_GATEWAYIP 192.168.11.1
214#define CONFIG_NETMASK 255.255.255.0
215
216#define CONFIG_LOADADDR 0x84000000
217#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
218#define CONFIG_BOOTFILE "fit.itb"
219
220#define CONFIG_CMDLINE_EDITING /* add command line history */
221
222#define CONFIG_BOOTCOMMAND "run $bootmode"
223
224#define CONFIG_ROOTPATH "/nfs/root/path"
225#define CONFIG_NFSBOOTCOMMAND \
226 "setenv bootargs $bootargs root=/dev/nfs rw " \
227 "nfsroot=$serverip:$rootpath " \
228 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
229 "tftpboot; bootm;"
230
231#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init"
232
233#define CONFIG_EXTRA_ENV_SETTINGS \
234 "netdev=eth0\0" \
235 "image_offset=0x00080000\0" \
236 "image_size=0x00f00000\0" \
237 "verify=n\0" \
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900238 "norboot=run add_default_bootargs;" \
239 "bootm $image_offset\0" \
240 "nandboot=run add_default_bootargs;" \
241 "nand read $loadaddr $image_offset $image_size;" \
242 "bootm\0" \
243 "add_default_bootargs=setenv bootargs $bootargs" \
244 " console=ttyS0,$baudrate\0" \
245
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900246/* Open Firmware flat tree */
247#define CONFIG_OF_LIBFDT
248
249#define CONFIG_HAVE_ARM_SECURE
250
251/* Memory Size & Mapping */
252#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
253
254#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
255/* Thre is no memory hole */
256#define CONFIG_NR_DRAM_BANKS 1
257#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
258#else
259#define CONFIG_NR_DRAM_BANKS 2
260#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
261#endif
262
263#define CONFIG_SYS_TEXT_BASE 0x84000000
264
Masahiro Yamadaf5d0b9b2014-12-06 00:03:22 +0900265#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
266#define CONFIG_SPL_TEXT_BASE 0x00040000
267#endif
268#if defined(CONFIG_MACH_PH1_PRO4)
269#define CONFIG_SPL_TEXT_BASE 0x00100000
270#endif
271
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900272#define CONFIG_BOARD_POSTCLK_INIT
Masahiro Yamadab67932e2014-11-11 22:18:22 +0900273
274#ifndef CONFIG_SPL_BUILD
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900275#define CONFIG_SKIP_LOWLEVEL_INIT
276#endif
277
278#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000)
279#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000)
280
Masahiro Yamada7e421d62014-12-18 19:11:02 +0900281#ifdef CONFIG_SPL_BUILD
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900282#define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000)
Masahiro Yamada7e421d62014-12-18 19:11:02 +0900283#else
284#define CONFIG_SYS_INIT_SP_ADDR ((CONFIG_SYS_TEXT_BASE) - 0x00001000)
285#endif
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900286
287#define CONFIG_SPL_FRAMEWORK
288#define CONFIG_SPL_NAND_SUPPORT
289
290#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
291#define CONFIG_SPL_LIBGENERIC_SUPPORT
292
293#define CONFIG_SPL_BOARD_INIT
294
295#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
296
297#endif /* __CONFIG_UNIPHIER_COMMON_H__ */