Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
| 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame^] | 9 | #include <altera.h> |
Pavel Machek | 99b9710 | 2014-07-14 14:14:17 +0200 | [diff] [blame] | 10 | #include <miiphy.h> |
| 11 | #include <netdev.h> |
Pavel Machek | de6da92 | 2014-09-09 14:03:28 +0200 | [diff] [blame] | 12 | #include <asm/arch/reset_manager.h> |
Pavel Machek | 45d6e67 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 13 | #include <asm/arch/system_manager.h> |
Pavel Machek | 4e73686 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 14 | #include <asm/arch/dwmmc.h> |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 15 | |
| 16 | DECLARE_GLOBAL_DATA_PTR; |
| 17 | |
Pavel Machek | 45d6e67 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 18 | static struct socfpga_system_manager *sysmgr_regs = |
| 19 | (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
| 20 | |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 21 | int dram_init(void) |
| 22 | { |
| 23 | gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); |
| 24 | return 0; |
| 25 | } |
Chin Liang See | 23f23f2 | 2014-06-10 02:23:45 -0500 | [diff] [blame] | 26 | |
Pavel Machek | 45d6e67 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 27 | /* |
| 28 | * DesignWare Ethernet initialization |
| 29 | */ |
| 30 | #ifdef CONFIG_DESIGNWARE_ETH |
| 31 | int cpu_eth_init(bd_t *bis) |
| 32 | { |
| 33 | #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS |
| 34 | const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; |
| 35 | #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS |
| 36 | const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; |
| 37 | #else |
| 38 | #error "Incorrect CONFIG_EMAC_BASE value!" |
| 39 | #endif |
| 40 | |
| 41 | /* Initialize EMAC. This needs to be done at least once per boot. */ |
| 42 | |
| 43 | /* |
| 44 | * Putting the EMAC controller to reset when configuring the PHY |
| 45 | * interface select at System Manager |
| 46 | */ |
| 47 | socfpga_emac_reset(1); |
| 48 | |
| 49 | /* Clearing emac0 PHY interface select to 0 */ |
| 50 | clrbits_le32(&sysmgr_regs->emacgrp_ctrl, |
| 51 | SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); |
| 52 | |
| 53 | /* configure to PHY interface select choosed */ |
| 54 | setbits_le32(&sysmgr_regs->emacgrp_ctrl, |
| 55 | SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); |
| 56 | |
| 57 | /* Release the EMAC controller from reset */ |
| 58 | socfpga_emac_reset(0); |
| 59 | |
| 60 | /* initialize and register the emac */ |
| 61 | return designware_initialize(CONFIG_EMAC_BASE, |
| 62 | CONFIG_PHY_INTERFACE_MODE); |
| 63 | } |
| 64 | #endif |
| 65 | |
Pavel Machek | 4e73686 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 66 | #ifdef CONFIG_DWMMC |
| 67 | /* |
| 68 | * Initializes MMC controllers. |
| 69 | * to override, implement board_mmc_init() |
| 70 | */ |
| 71 | int cpu_mmc_init(bd_t *bis) |
| 72 | { |
| 73 | return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, |
| 74 | CONFIG_HPS_SDMMC_BUSWIDTH, 0); |
| 75 | } |
| 76 | #endif |
| 77 | |
Chin Liang See | 23f23f2 | 2014-06-10 02:23:45 -0500 | [diff] [blame] | 78 | #if defined(CONFIG_DISPLAY_CPUINFO) |
| 79 | /* |
| 80 | * Print CPU information |
| 81 | */ |
| 82 | int print_cpuinfo(void) |
| 83 | { |
Pavel Machek | d5a3d3c | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 84 | puts("CPU: Altera SoCFPGA Platform\n"); |
Chin Liang See | 23f23f2 | 2014-06-10 02:23:45 -0500 | [diff] [blame] | 85 | return 0; |
| 86 | } |
| 87 | #endif |
| 88 | |
| 89 | #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ |
| 90 | defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) |
| 91 | int overwrite_console(void) |
| 92 | { |
| 93 | return 0; |
| 94 | } |
| 95 | #endif |
| 96 | |
Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame^] | 97 | #ifdef CONFIG_FPGA |
| 98 | /* |
| 99 | * FPGA programming support for SoC FPGA Cyclone V |
| 100 | */ |
| 101 | static Altera_desc altera_fpga[] = { |
| 102 | { |
| 103 | /* Family */ |
| 104 | Altera_SoCFPGA, |
| 105 | /* Interface type */ |
| 106 | fast_passive_parallel, |
| 107 | /* No limitation as additional data will be ignored */ |
| 108 | -1, |
| 109 | /* No device function table */ |
| 110 | NULL, |
| 111 | /* Base interface address specified in driver */ |
| 112 | NULL, |
| 113 | /* No cookie implementation */ |
| 114 | 0 |
| 115 | }, |
| 116 | }; |
| 117 | |
| 118 | /* add device descriptor to FPGA device table */ |
| 119 | static void socfpga_fpga_add(void) |
| 120 | { |
| 121 | int i; |
| 122 | fpga_init(); |
| 123 | for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) |
| 124 | fpga_add(fpga_altera, &altera_fpga[i]); |
| 125 | } |
| 126 | #else |
| 127 | static inline void socfpga_fpga_add(void) {} |
| 128 | #endif |
| 129 | |
Pavel Machek | de6da92 | 2014-09-09 14:03:28 +0200 | [diff] [blame] | 130 | int arch_cpu_init(void) |
| 131 | { |
| 132 | /* |
| 133 | * If the HW watchdog is NOT enabled, make sure it is not running, |
| 134 | * for example because it was enabled in the preloader. This might |
| 135 | * trigger a watchdog-triggered reboot of Linux kernel later. |
| 136 | */ |
| 137 | #ifndef CONFIG_HW_WATCHDOG |
| 138 | socfpga_watchdog_reset(); |
| 139 | #endif |
| 140 | return 0; |
| 141 | } |
| 142 | |
Chin Liang See | 23f23f2 | 2014-06-10 02:23:45 -0500 | [diff] [blame] | 143 | int misc_init_r(void) |
| 144 | { |
Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame^] | 145 | /* Add device descriptor to FPGA device table */ |
| 146 | socfpga_fpga_add(); |
Chin Liang See | 23f23f2 | 2014-06-10 02:23:45 -0500 | [diff] [blame] | 147 | return 0; |
| 148 | } |