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Tim Schendekehl14c32612011-11-01 23:55:01 +00001/*
2 * (C) Copyright 2011
3 * egnite GmbH <info@egnite.de>
4 *
5 * (C) Copyright 2010
6 * Ole Reinhardt <ole.reinhardt@thermotemp.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * Ethernut 5 general board support
29 *
30 * Ethernut is an open source hardware and software project for
31 * embedded Ethernet devices. Hardware layouts and CAD files are
32 * freely available under BSD-like license.
33 *
34 * Ethernut 5 is the first member of the Ethernut board family
35 * with U-Boot and Linux support. This implementation is based
36 * on the original work done by Ole Reinhardt, but heavily modified
37 * to support additional features and the latest board revision 5.0F.
38 *
39 * Main board components are by default:
40 *
41 * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
42 * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
43 * 512 MBytes Micron MT29F4G08ABADA NAND Flash
44 * 4 MBytes Atmel AT45DB321D DataFlash
45 * SMSC LAN8710 Ethernet PHY
46 * Atmel ATmega168 MCU used for power management
47 * Linear Technology LTC4411 PoE controller
48 *
49 * U-Boot relevant board interfaces are:
50 *
51 * 100 Mbit Ethernet with IEEE 802.3af PoE
52 * RS-232 serial port
53 * USB host and device
54 * MMC/SD-Card slot
55 * Expansion port with I2C, SPI and more...
56 *
57 * Typically the U-Boot image is loaded from serial DataFlash into
58 * SDRAM by the samboot boot loader, which is located in internal
59 * NOR Flash and provides all essential initializations like CPU
60 * and peripheral clocks and, of course, the SDRAM configuration.
61 *
62 * For testing purposes it is also possibly to directly transfer
63 * the image into SDRAM via JTAG. A tested configuration exists
64 * for the Turtelizer 2 hardware dongle and the OpenOCD software.
65 * In this case the latter will do the basic hardware configuration
66 * via its reset-init script.
67 *
68 * For additional information visit the project home page at
69 * http://www.ethernut.de/
70 */
71
72#include <common.h>
73#include <net.h>
74#include <netdev.h>
75#include <miiphy.h>
76#include <i2c.h>
77#include <spi.h>
78#include <dataflash.h>
79#include <mmc.h>
80
81#include <asm/arch/at91sam9260.h>
82#include <asm/arch/at91sam9260_matrix.h>
83#include <asm/arch/at91sam9_smc.h>
84#include <asm/arch/at91_common.h>
85#include <asm/arch/at91_pmc.h>
86#include <asm/arch/at91_spi.h>
87#include <asm/arch/gpio.h>
88#include <asm/io.h>
89
90#include "ethernut5_pwrman.h"
91
92DECLARE_GLOBAL_DATA_PTR;
93
94AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
95
96struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
97 {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}
98};
99
100/*
101 * In fact we have 7 partitions, but u-boot supports 5 only. This is
102 * no big deal, because the first partition is reserved for applications
103 * and the last one is used by Nut/OS. Both need not to be visible here.
104 */
105dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
106 { 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" },
107 { 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" },
108 { 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" },
109 { 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" },
110 { 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" }
111};
112
113/*
114 * This is called last during early initialization. Most of the basic
115 * hardware interfaces are up and running.
116 *
117 * The SDRAM hardware has been configured by the first stage boot loader.
118 * We only need to announce its size, using u-boot's memory check.
119 */
120int dram_init(void)
121{
122 gd->ram_size = get_ram_size(
123 (void *)CONFIG_SYS_SDRAM_BASE,
124 CONFIG_SYS_SDRAM_SIZE);
125 return 0;
126}
127
128#ifdef CONFIG_CMD_NAND
129static void ethernut5_nand_hw_init(void)
130{
131 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
132 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
133 unsigned long csa;
134
135 /* Assign CS3 to NAND/SmartMedia Interface */
136 csa = readl(&matrix->ebicsa);
137 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
138 writel(csa, &matrix->ebicsa);
139
140 /* Configure SMC CS3 for NAND/SmartMedia */
141 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
142 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
143 &smc->cs[3].setup);
144 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
145 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
146 &smc->cs[3].pulse);
147 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
148 &smc->cs[3].cycle);
149 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
150 AT91_SMC_MODE_EXNW_DISABLE |
151 AT91_SMC_MODE_DBW_8 |
152 AT91_SMC_MODE_TDF_CYCLE(2),
153 &smc->cs[3].mode);
154
155#ifdef CONFIG_SYS_NAND_READY_PIN
156 /* Ready pin is optional. */
157 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
158#endif
159 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
160}
161#endif
162
163/*
164 * This is called first during late initialization.
165 */
166int board_init(void)
167{
168 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
169
170 /* Enable clocks for all PIOs */
171 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
172 (1 << ATMEL_ID_PIOC),
173 &pmc->pcer);
174 /* Set adress of boot parameters. */
175 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
176 /* Initialize UARTs and power management. */
177 at91_seriald_hw_init();
178 ethernut5_power_init();
179#ifdef CONFIG_CMD_NAND
180 ethernut5_nand_hw_init();
181#endif
182#ifdef CONFIG_HAS_DATAFLASH
183 at91_spi0_hw_init(1 << 0);
184#endif
185 return 0;
186}
187
188#ifdef CONFIG_MACB
189/*
190 * This is optionally called last during late initialization.
191 */
192int board_eth_init(bd_t *bis)
193{
194 const char *devname;
195 unsigned short mode;
196 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
197
198 /* Enable on-chip EMAC clock. */
199 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
200 /* Need to reset PHY via power management. */
201 ethernut5_phy_reset();
202 /* Set peripheral pins. */
203 at91_macb_hw_init();
204 /* Basic EMAC initialization. */
205 if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
206 return -1;
207 /*
208 * Early board revisions have a pull-down at the PHY's MODE0
209 * strap pin, which forces the PHY into power down. Here we
210 * switch to all-capable mode.
211 */
212 devname = miiphy_get_current_dev();
213 if (miiphy_read(devname, 0, 18, &mode) == 0) {
214 /* Set mode[2:0] to 0b111. */
215 mode |= 0x00E0;
216 miiphy_write(devname, 0, 18, mode);
217 /* Soft reset overrides strap pins. */
218 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
219 }
220 /* Sync environment with network devices, needed for nfsroot. */
221 return eth_init(gd->bd);
222}
223#endif
224
225#ifdef CONFIG_GENERIC_ATMEL_MCI
226int board_mmc_init(bd_t *bd)
227{
228 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
229
230 /* Enable MCI clock. */
231 writel(1 << ATMEL_ID_MCI, &pmc->pcer);
232 /* Initialize MCI hardware. */
233 at91_mci_hw_init();
234 /* Register the device. */
235 return atmel_mci_init((void *)ATMEL_BASE_MCI);
236}
237
prabhakar.csengg@gmail.com2271e7c2012-02-23 01:53:40 +0000238int board_mmc_getcd(struct mmc *mmc)
Tim Schendekehl14c32612011-11-01 23:55:01 +0000239{
prabhakar.csengg@gmail.com2271e7c2012-02-23 01:53:40 +0000240 return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
Tim Schendekehl14c32612011-11-01 23:55:01 +0000241}
242#endif
243
244#ifdef CONFIG_ATMEL_SPI
245/*
246 * Note, that u-boot uses different code for SPI bus access. While
247 * memory routines use automatic chip select control, the serial
248 * flash support requires 'manual' GPIO control. Thus, we switch
249 * modes.
250 */
251void spi_cs_activate(struct spi_slave *slave)
252{
253 /* Enable NPCS0 in GPIO mode. This disables peripheral control. */
254 at91_set_pio_output(AT91_PIO_PORTA, 3, 0);
255}
256
257void spi_cs_deactivate(struct spi_slave *slave)
258{
259 /* Disable NPCS0 in GPIO mode. */
260 at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
261 /* Switch back to peripheral chip select control. */
262 at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
263}
264
265int spi_cs_is_valid(unsigned int bus, unsigned int cs)
266{
267 return bus == 0 && cs == 0;
268}
269#endif