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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marian Balakowicz991425f2006-03-14 16:24:38 +01002/*
3 * (C) Copyright 2006
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Marian Balakowicz991425f2006-03-14 16:24:38 +01005 */
6
7#include <common.h>
8#include <ioports.h>
9#include <mpc83xx.h>
10#include <asm/mpc8349_pci.h>
11#include <i2c.h>
Ben Warren80ddd222008-01-16 22:37:42 -050012#include <spi.h>
Marian Balakowicz991425f2006-03-14 16:24:38 +010013#include <miiphy.h>
York Sun5614e712013-09-30 09:22:09 -070014#ifdef CONFIG_SYS_FSL_DDR2
15#include <fsl_ddr_sdram.h>
York Sund4b91062011-08-26 11:32:45 -070016#else
Marian Balakowicz991425f2006-03-14 16:24:38 +010017#include <spd_sdram.h>
York Sund4b91062011-08-26 11:32:45 -070018#endif
Jon Loeligera30a5492008-03-04 10:03:03 -060019
Kim Phillipsb3458d22007-12-20 15:57:28 -060020#if defined(CONFIG_OF_LIBFDT)
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090021#include <linux/libfdt.h>
Kim Phillipsbf0b5422006-11-01 00:10:40 -060022#endif
23
Simon Glass088454c2017-03-31 08:40:25 -060024DECLARE_GLOBAL_DATA_PTR;
25
Marian Balakowicz991425f2006-03-14 16:24:38 +010026int fixed_sdram(void);
27void sdram_init(void);
28
Peter Tyser0f898602009-05-22 17:23:24 -050029#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
Marian Balakowicz991425f2006-03-14 16:24:38 +010030void ddr_enable_ecc(unsigned int dram_size);
31#endif
32
33int board_early_init_f (void)
34{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035 volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
Marian Balakowicz991425f2006-03-14 16:24:38 +010036
37 /* Enable flash write */
38 bcsr[1] &= ~0x01;
39
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
Kumar Gala8fe9bf62006-04-20 13:45:32 -050041 /* Use USB PHY on SYS board */
42 bcsr[5] |= 0x02;
43#endif
44
Marian Balakowicz991425f2006-03-14 16:24:38 +010045 return 0;
46}
47
48#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
49
Simon Glassf1683aa2017-04-06 12:47:05 -060050int dram_init(void)
Marian Balakowicz991425f2006-03-14 16:24:38 +010051{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
York Sund4b91062011-08-26 11:32:45 -070053 phys_size_t msize = 0;
Marian Balakowicz991425f2006-03-14 16:24:38 +010054
55 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
Simon Glass088454c2017-03-31 08:40:25 -060056 return -ENXIO;
Marian Balakowicz991425f2006-03-14 16:24:38 +010057
58 /* DDR SDRAM - Main SODIMM */
Mario Six8a81bfd2019-01-21 09:18:15 +010059 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
Marian Balakowicz991425f2006-03-14 16:24:38 +010060#if defined(CONFIG_SPD_EEPROM)
York Sun5614e712013-09-30 09:22:09 -070061#ifndef CONFIG_SYS_FSL_DDR2
York Sund4b91062011-08-26 11:32:45 -070062 msize = spd_sdram() * 1024 * 1024;
63#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
64 ddr_enable_ecc(msize);
65#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +010066#else
York Sund4b91062011-08-26 11:32:45 -070067 msize = fsl_ddr_sdram();
68#endif
69#else
70 msize = fixed_sdram() * 1024 * 1024;
Marian Balakowicz991425f2006-03-14 16:24:38 +010071#endif
72 /*
73 * Initialize SDRAM if it is on local bus.
74 */
75 sdram_init();
76
Simon Glass088454c2017-03-31 08:40:25 -060077 /* set total bus SDRAM size(bytes) -- DDR */
78 gd->ram_size = msize;
79
80 return 0;
Marian Balakowicz991425f2006-03-14 16:24:38 +010081}
82
83#if !defined(CONFIG_SPD_EEPROM)
84/*************************************************************************
85 * fixed sdram init -- doesn't use serial presence detect.
86 ************************************************************************/
87int fixed_sdram(void)
88{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
Joe Hershberger2e651b22011-10-11 23:57:31 -050090 u32 msize = CONFIG_SYS_DDR_SIZE;
91 u32 ddr_size = msize << 20; /* DDR size in bytes */
92 u32 ddr_size_log2 = __ilog2(ddr_size);
Marian Balakowicz991425f2006-03-14 16:24:38 +010093
Mario Six133ec602019-01-21 09:18:16 +010094 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
Marian Balakowicz991425f2006-03-14 16:24:38 +010095 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#if (CONFIG_SYS_DDR_SIZE != 256)
Marian Balakowicz991425f2006-03-14 16:24:38 +010098#warning Currenly any ddr size other than 256 is not supported
99#endif
Xie Xiaobod61853c2007-02-14 18:27:17 +0800100#ifdef CONFIG_DDR_II
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
102 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
103 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
104 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
105 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
106 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
107 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
108 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
109 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
110 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
111 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
112 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800113#else
Joe Hershberger2e651b22011-10-11 23:57:31 -0500114
Mario Six133ec602019-01-21 09:18:16 +0100115#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
Joe Hershberger2e651b22011-10-11 23:57:31 -0500116#warning Chip select bounds is only configurable in 16MB increments
117#endif
118 im->ddr.csbnds[2].csbnds =
Mario Six133ec602019-01-21 09:18:16 +0100119 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
120 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
Joe Hershberger2e651b22011-10-11 23:57:31 -0500121 CSBNDS_EA_SHIFT) & CSBNDS_EA);
122 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100123
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200124 /* currently we use only one CS, so disable the other banks */
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100125 im->ddr.cs_config[0] = 0;
126 im->ddr.cs_config[1] = 0;
127 im->ddr.cs_config[3] = 0;
128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
130 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200131
Marian Balakowicz991425f2006-03-14 16:24:38 +0100132 im->ddr.sdram_cfg =
133 SDRAM_CFG_SREN
134#if defined(CONFIG_DDR_2T_TIMING)
135 | SDRAM_CFG_2T_EN
136#endif
137 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100138#if defined (CONFIG_DDR_32BIT)
139 /* for 32-bit mode burst length is 8 */
140 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
141#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800145#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100146 udelay(200);
147
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100148 /* enable DDR controller */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100149 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100150 return msize;
151}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#endif/*!CONFIG_SYS_SPD_EEPROM*/
Marian Balakowicz991425f2006-03-14 16:24:38 +0100153
154
155int checkboard (void)
156{
Ira W. Snyder447ad572008-08-22 11:00:15 -0700157 /*
158 * Warning: do not read the BCSR registers here
159 *
160 * There is a timing bug in the 8349E and 8349EA BCSR code
161 * version 1.2 (read from BCSR 11) that will cause the CFI
162 * flash initialization code to overwrite BCSR 0, disabling
163 * the serial ports and gigabit ethernet
164 */
165
Marian Balakowicz991425f2006-03-14 16:24:38 +0100166 puts("Board: Freescale MPC8349EMDS\n");
167 return 0;
168}
169
Marian Balakowicz991425f2006-03-14 16:24:38 +0100170/*
171 * if MPC8349EMDS is soldered with SDRAM
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#if defined(CONFIG_SYS_BR2_PRELIM) \
174 && defined(CONFIG_SYS_OR2_PRELIM) \
175 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
176 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100177/*
178 * Initialize SDRAM memory on the Local Bus.
179 */
180
181void sdram_init(void)
182{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500184 volatile fsl_lbc_t *lbc = &immap->im_lbc;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Mario Six42c9a492019-01-21 09:18:17 +0100186 const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
187 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
188 LSDMR_WRC3 | LSDMR_CL3;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100189 /*
190 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
191 */
192
193 /* setup mtrpt, lsrt and lbcr for LB bus */
Mario Six42c9a492019-01-21 09:18:17 +0100194 lbc->lbcr = 0x00000000;
195 /* LB refresh timer prescal, 266MHz/32 */
196 lbc->mrtpr = 0x20000000;
197 /* LB sdram refresh timer, about 6us */
198 lbc->lsrt = 0x32000000;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100199 asm("sync");
200
201 /*
202 * Configure the SDRAM controller Machine Mode Register.
203 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100204
Mario Six42c9a492019-01-21 09:18:17 +0100205 /* 0x40636733; normal operation */
206 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
207
208 /* 0x68636733; precharge all the banks */
209 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100210 asm("sync");
211 *sdram_addr = 0xff;
212 udelay(100);
213
Mario Six42c9a492019-01-21 09:18:17 +0100214 /* 0x48636733; auto refresh */
215 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100216 asm("sync");
217 /*1 times*/
218 *sdram_addr = 0xff;
219 udelay(100);
220 /*2 times*/
221 *sdram_addr = 0xff;
222 udelay(100);
223 /*3 times*/
224 *sdram_addr = 0xff;
225 udelay(100);
226 /*4 times*/
227 *sdram_addr = 0xff;
228 udelay(100);
229 /*5 times*/
230 *sdram_addr = 0xff;
231 udelay(100);
232 /*6 times*/
233 *sdram_addr = 0xff;
234 udelay(100);
235 /*7 times*/
236 *sdram_addr = 0xff;
237 udelay(100);
238 /*8 times*/
239 *sdram_addr = 0xff;
240 udelay(100);
241
242 /* 0x58636733; mode register write operation */
Mario Six42c9a492019-01-21 09:18:17 +0100243 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100244 asm("sync");
245 *sdram_addr = 0xff;
246 udelay(100);
247
Mario Six42c9a492019-01-21 09:18:17 +0100248 /* 0x40636733; normal operation */
249 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100250 asm("sync");
251 *sdram_addr = 0xff;
252 udelay(100);
253}
254#else
255void sdram_init(void)
256{
Marian Balakowicz991425f2006-03-14 16:24:38 +0100257}
258#endif
Marian Balakowiczd326f4a2006-03-16 15:19:35 +0100259
Ben Warren80ddd222008-01-16 22:37:42 -0500260/*
261 * The following are used to control the SPI chip selects for the SPI command.
262 */
Ben Warrenf8cc3122008-06-08 23:28:33 -0700263#ifdef CONFIG_MPC8XXX_SPI
Ben Warren80ddd222008-01-16 22:37:42 -0500264
265#define SPI_CS_MASK 0x80000000
266
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200267int spi_cs_is_valid(unsigned int bus, unsigned int cs)
268{
269 return bus == 0 && cs == 0;
270}
271
272void spi_cs_activate(struct spi_slave *slave)
Ben Warren80ddd222008-01-16 22:37:42 -0500273{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
Ben Warren80ddd222008-01-16 22:37:42 -0500275
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200276 iopd->dat &= ~SPI_CS_MASK;
Ben Warren80ddd222008-01-16 22:37:42 -0500277}
278
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200279void spi_cs_deactivate(struct spi_slave *slave)
280{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
Ben Warren80ddd222008-01-16 22:37:42 -0500282
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200283 iopd->dat |= SPI_CS_MASK;
284}
Jagan Teki35f9d9b2018-11-24 14:31:12 +0530285#endif
Ben Warren80ddd222008-01-16 22:37:42 -0500286
Kim Phillips3fde9e82007-08-15 22:30:33 -0500287#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glasse895a4b2014-10-23 18:58:47 -0600288int ft_board_setup(void *blob, bd_t *bd)
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600289{
Kim Phillips3fde9e82007-08-15 22:30:33 -0500290 ft_cpu_setup(blob, bd);
291#ifdef CONFIG_PCI
292 ft_pci_setup(blob, bd);
293#endif
Simon Glasse895a4b2014-10-23 18:58:47 -0600294
295 return 0;
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600296}
297#endif