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Wolfgang Denk7ce343e2006-10-09 00:48:57 +02001/*
2 * Copyright (C) 2006 Embedded Planet, LLC.
3 *
4 * U-Boot configuration for Embedded Planet EP82xxM boards.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28#define CONFIG_MPC8260
29#define CPU_ID_STR "MPC8270"
30
Wolfgang Denkf836e412006-10-20 16:12:14 +020031#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020032 /* 256MB SDRAM / 64MB FLASH */
33
Wolfgang Denk2ae18242010-10-06 09:05:45 +020034#define CONFIG_SYS_TEXT_BASE 0xFFF00000
35
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020036#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
37
38/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
39#define CONFIG_ENV_OVERWRITE
40
41/*
42 * Select serial console configuration
43 *
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
46 * for SCC).
47 */
48#define CONFIG_CONS_ON_SMC /* Console is on SMC */
49#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50#undef CONFIG_CONS_NONE /* It's not on external UART */
51#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
52
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_BCSR 0xFA000000
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020054
55/*
56 * Select ethernet configuration
57 *
58 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
59 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
60 * SCC, 1-3 for FCC)
61 *
62 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
Jon Loeliger639221c2007-07-09 17:15:49 -050063 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
64 * must be unset.
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020065 */
66#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
67#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
68#undef CONFIG_ETHER_NONE /* No external Ethernet */
69
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020070
71#define CONFIG_ETHER_ON_FCC2
72#define CONFIG_ETHER_ON_FCC3
73
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
75#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
76#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
77#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020078
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_CPMFCR_RAMTYPE 0
80#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020081
82#define CONFIG_MII /* MII PHY management */
83#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
84
85/*
86 * GPIO pins used for bit-banged MII communications
87 */
88#define MDIO_PORT 0 /* Not used - implemented in BCSR */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +020089
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
91#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
92#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
95 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
98 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
Wolfgang Denk7ce343e2006-10-09 00:48:57 +020099
100#define MIIDELAY udelay(1)
101
102
103#ifndef CONFIG_8260_CLKIN
104#define CONFIG_8260_CLKIN 66000000 /* in Hz */
105#endif
106
107#define CONFIG_BAUDRATE 115200
108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200110
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200111
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500112/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500113 * BOOTP options
114 */
115#define CONFIG_BOOTP_BOOTFILESIZE
116#define CONFIG_BOOTP_BOOTPATH
117#define CONFIG_BOOTP_GATEWAY
118#define CONFIG_BOOTP_HOSTNAME
119
120
121/*
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500122 * Command line configuration.
123 */
124#include <config_cmd_default.h>
125
126
127#define CONFIG_CMD_DHCP
128#define CONFIG_CMD_ECHO
129#define CONFIG_CMD_I2C
130#define CONFIG_CMD_IMMAP
131#define CONFIG_CMD_MII
132#define CONFIG_CMD_PING
133#define CONFIG_CMD_DATE
134#define CONFIG_CMD_DTT
135#define CONFIG_CMD_EEPROM
136#define CONFIG_CMD_PCI
137#define CONFIG_CMD_DIAG
138
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200139
140#define CONFIG_ETHADDR 00:10:EC:00:88:65
141#define CONFIG_HAS_ETH1
142#define CONFIG_ETH1ADDR 00:10:EC:80:88:65
143#define CONFIG_IPADDR 10.0.0.245
144#define CONFIG_HOSTNAME EP82xxM
145#define CONFIG_SERVERIP 10.0.0.26
146#define CONFIG_GATEWAYIP 10.0.0.1
147#define CONFIG_NETMASK 255.255.255.0
148#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200149#define CONFIG_ENV_IN_OWN_SECT 1
Wolfgang Denk8078f1a2006-10-28 02:28:02 +0200150#define CONFIG_AUTO_COMPLETE 1
Heiko Schocher48690d82010-07-20 17:45:02 +0200151#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3"
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200152
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500153#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200154#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
155#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
156#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
157#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
158#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
159#endif
160
161#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
162#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
163
164/*
165 * Miscellaneous configurable options
166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_HUSH_PARSER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_LONGHELP /* undef to save memory */
169#define CONFIG_SYS_PROMPT "ep82xxm=> " /* Monitor Command Prompt */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500170#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200172#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200174#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
176#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
177#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
180#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200187
188/*-----------------------------------------------------------------------
189 * Environment
190 *----------------------------------------------------------------------*/
191/*
192 * Define here the location of the environment variables (FLASH or EEPROM).
193 * Note: DENX encourages to use redundant environment in FLASH.
194 */
195#if 1
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200196#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200197#else
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200198#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200199#endif
200
201/*-----------------------------------------------------------------------
202 * FLASH related
203 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_BASE 0xFC000000
205#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200206#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
208#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
209#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200210
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200211#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200212#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200214#endif /* CONFIG_ENV_IS_IN_FLASH */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200215
216/*-----------------------------------------------------------------------
217 * I2C
218 *----------------------------------------------------------------------*/
219/* EEPROM Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_EEPROM_SIZE 0x1000
221#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
222#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
223#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
224#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200225
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200226#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200227#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
228#define CONFIG_ENV_OFFSET 0x0
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200229#endif /* CONFIG_ENV_IS_IN_EEPROM */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200230
231/* RTC Configuration */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200232#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200234#define CONFIG_M41T11_BASE_YEAR 1900
235
236/* I2C SYSMON (LM75) */
237#define CONFIG_DTT_LM75 1
238#define CONFIG_DTT_SENSORS {0}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_DTT_MAX_TEMP 70
240#define CONFIG_SYS_DTT_LOW_TEMP -30
241#define CONFIG_SYS_DTT_HYSTERESIS 3
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200242
243/*-----------------------------------------------------------------------
244 * NVRAM Configuration
245 *-----------------------------------------------------------------------
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000
248#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200249
250
251/*-----------------------------------------------------------------------
252 * PCI stuff
253 *-----------------------------------------------------------------------
254 */
255/* General PCI */
256#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000257#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200258#define CONFIG_PCI_PNP /* do pci plug-and-play */
259#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
260#define CONFIG_PCI_BOOTDELAY 0
261
262/* PCI Memory map (if different from default map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
264#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
265#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200266 PICMR_PREFETCH_EN)
267
268/*
269 * These are the windows that allow the CPU to access PCI address space.
270 * All three PCI master windows, which allow the CPU to access PCI
271 * prefetch, non prefetch, and IO space (see below), must all fit within
272 * these windows.
273 */
274
275/*
276 * Master window that allows the CPU to access PCI Memory (prefetch).
277 * This window will be setup with the second set of Outbound ATU registers
278 * in the bridge.
279 */
280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
282#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
283#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
284#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
285#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200286
287/*
288 * Master window that allows the CPU to access PCI Memory (non-prefetch).
289 * This window will be setup with the second set of Outbound ATU registers
290 * in the bridge.
291 */
292
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
294#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
295#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
296#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
297#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200298
299/*
300 * Master window that allows the CPU to access PCI IO space.
301 * This window will be setup with the first set of Outbound ATU registers
302 * in the bridge.
303 */
304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
306#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
307#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
308#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
309#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200310
311
312/* PCIBR0 - for PCI IO*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
314#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200315/* PCIBR1 - prefetch and non-prefetch regions joined together */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
317#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200318
319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_DIRECT_FLASH_TFTP
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200321
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500322#if defined(CONFIG_CMD_JFFS2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_JFFS2_FIRST_BANK 0
324#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
325#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
326#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
327#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
328#define CONFIG_SYS_JFFS_CUSTOM_PART
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500329#endif
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200330
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500331#if defined(CONFIG_CMD_I2C)
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200332#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
334#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500335#endif
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200336
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200337#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
339#define CONFIG_SYS_RAMBOOT
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200340#endif
341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
345#define CONFIG_SYS_IMMR 0xF0000000
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200348#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200349#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200351
352
353/* Hard reset configuration word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200355/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_HRCW_SLAVE1 0
357#define CONFIG_SYS_HRCW_SLAVE2 0
358#define CONFIG_SYS_HRCW_SLAVE3 0
359#define CONFIG_SYS_HRCW_SLAVE4 0
360#define CONFIG_SYS_HRCW_SLAVE5 0
361#define CONFIG_SYS_HRCW_SLAVE6 0
362#define CONFIG_SYS_HRCW_SLAVE7 0
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200363
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
365#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200366
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500368#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200370#endif
371
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_HID0_INIT 0
373#define CONFIG_SYS_HID0_FINAL 0
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_HID2 0
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_SIUMCR 0x02610000
378#define CONFIG_SYS_SYPCR 0xFFFF0689
379#define CONFIG_SYS_BCR 0x8080E000
380#define CONFIG_SYS_SCCR 0x00000001
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200381
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_RMR 0
383#define CONFIG_SYS_TMCNTSC 0x000000C3
384#define CONFIG_SYS_PISCR 0x00000083
385#define CONFIG_SYS_RCCR 0
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200386
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_MPTPR 0x0A00
388#define CONFIG_SYS_PSDMR 0xC432246E
389#define CONFIG_SYS_PSRT 0x32
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200390
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_SDRAM_BASE 0x00000000
392#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
393#define CONFIG_SYS_SDRAM_OR 0xF0002900
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200394
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
396#define CONFIG_SYS_OR0_PRELIM 0xFC000882
397#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_BCSR | 0x00001001)
398#define CONFIG_SYS_OR4_PRELIM 0xFFF00050
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200399
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
Wolfgang Denk7ce343e2006-10-09 00:48:57 +0200401
402#endif /* __CONFIG_H */