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Prabhakar Kushwaha9cc2c472015-03-20 19:28:22 -07001/*
2 * Copyright (C) 2015 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LDPAA_WRIOP_H
8#define __LDPAA_WRIOP_H
9
10 #include <phy.h>
11
12enum wriop_port {
13 WRIOP1_DPMAC1 = 1,
14 WRIOP1_DPMAC2,
15 WRIOP1_DPMAC3,
16 WRIOP1_DPMAC4,
17 WRIOP1_DPMAC5,
18 WRIOP1_DPMAC6,
19 WRIOP1_DPMAC7,
20 WRIOP1_DPMAC8,
21 WRIOP1_DPMAC9,
22 WRIOP1_DPMAC10,
23 WRIOP1_DPMAC11,
24 WRIOP1_DPMAC12,
25 WRIOP1_DPMAC13,
26 WRIOP1_DPMAC14,
27 WRIOP1_DPMAC15,
28 WRIOP1_DPMAC16,
29 WRIOP1_DPMAC17,
30 WRIOP1_DPMAC18,
31 WRIOP1_DPMAC19,
32 WRIOP1_DPMAC20,
33 WRIOP1_DPMAC21,
34 WRIOP1_DPMAC22,
35 WRIOP1_DPMAC23,
36 WRIOP1_DPMAC24,
37 NUM_WRIOP_PORTS,
38};
39
40struct wriop_dpmac_info {
41 u8 enabled;
42 u8 id;
Prabhakar Kushwaha9cc2c472015-03-20 19:28:22 -070043 u8 board_mux;
Prabhakar Kushwahaf9127a02015-11-04 12:25:56 +053044 int phy_addr;
Prabhakar Kushwaha9cc2c472015-03-20 19:28:22 -070045 void *phy_regs;
46 phy_interface_t enet_if;
47 struct phy_device *phydev;
48 struct mii_dev *bus;
49};
50
51extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
52
53#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0"
54#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1"
55
56void wriop_init_dpmac(int, int, int);
57void wriop_disable_dpmac(int);
58void wriop_enable_dpmac(int);
Prabhakar Kushwahaf9127a02015-11-04 12:25:56 +053059u8 wriop_is_enabled_dpmac(int dpmac_id);
Prabhakar Kushwaha9cc2c472015-03-20 19:28:22 -070060void wriop_set_mdio(int, struct mii_dev *);
61struct mii_dev *wriop_get_mdio(int);
62void wriop_set_phy_address(int, int);
63int wriop_get_phy_address(int);
64void wriop_set_phy_dev(int, struct phy_device *);
65struct phy_device *wriop_get_phy_dev(int);
66phy_interface_t wriop_get_enet_if(int);
67
68void wriop_dpmac_disable(int);
69void wriop_dpmac_enable(int);
70phy_interface_t wriop_dpmac_enet_if(int, int);
71#endif /* __LDPAA_WRIOP_H */