Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 1 | Introduction |
| 2 | ============ |
| 3 | |
| 4 | HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: - |
| 5 | * HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz. |
| 6 | * ARM Mali 450-MP4 GPU |
| 7 | * 1GB 800MHz LPDDR3 DRAM |
| 8 | * 4GB eMMC Flash Storage |
| 9 | * microSD |
| 10 | * 802.11a/b/g/n WiFi, Bluetooth |
| 11 | |
| 12 | The HiKey schematic can be found here: - |
| 13 | https://github.com/96boards/documentation/blob/master/hikey/96Boards-Hikey-Rev-A1.pdf |
| 14 | |
| 15 | A SoC datasheet can be found here: - |
| 16 | https://github.com/96boards/documentation/blob/master/hikey/ |
| 17 | Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf |
| 18 | |
| 19 | Currently the u-boot port supports: - |
| 20 | * USB |
| 21 | * eMMC |
| 22 | * SD card |
| 23 | * GPIO |
| 24 | |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 25 | The HiKey U-Boot port has been tested with l-loader, booting ATF, which then boots |
| 26 | U-Boot as the bl33.bin executable. |
| 27 | |
| 28 | Compile from source |
| 29 | =================== |
| 30 | |
| 31 | First get all the sources |
| 32 | |
| 33 | > mkdir -p ~/hikey/src ~/hikey/bin |
| 34 | > cd ~/hikey/src |
| 35 | > git clone https://github.com/96boards/edk2.git |
| 36 | > git clone https://github.com/96boards/arm-trusted-firmware.git |
| 37 | > git clone https://github.com/96boards/l-loader.git |
| 38 | > git clone https://github.com/96boards/burn-boot.git |
| 39 | |
| 40 | Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source. |
| 41 | The latest version can be obtained from the edk2 repo. |
| 42 | |
| 43 | > cp edk2/HisiPkg/HiKeyPkg/NonFree/mcuimage.bin ~/hikey/bin/ |
| 44 | |
| 45 | Get nvme.img binary (check this link is still the latest) |
| 46 | > wget -P ~/hikey/bin https://builds.96boards.org/releases/reference-platform/debian/hikey/16.03/bootloader/nvme.img |
| 47 | |
| 48 | Compile U-Boot |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 49 | ============== |
| 50 | |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 51 | > cd ~/hikey/src/u-boot |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 52 | > make CROSS_COMPILE=aarch64-linux-gnu- hikey_config |
| 53 | > make CROSS_COMPILE=aarch64-linux-gnu- |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 54 | > cp u-boot.bin ~/hikey/bin |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 55 | |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 56 | Compile ARM Trusted Firmware (ATF) |
| 57 | ================================== |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 58 | |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 59 | > cd ~/hikey/src/atf |
| 60 | > make CROSS_COMPILE=aarch64-linux-gnu- all fip \ |
| 61 | BL30=~/hikey/bin/mcuimage.bin \ |
| 62 | BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 63 | |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 64 | Copy resulting binaries |
| 65 | > cp build/hikey/debug/bl1.bin ~/hikey/bin |
| 66 | > cp build/hikey/debug/fip.bin ~/hikey/bin |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 67 | |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 68 | Compile l-loader |
| 69 | =============== |
| 70 | > cd ~/hikey/l-loader |
| 71 | > make BL1=~/hikey/bin/bl1.bin all |
| 72 | > cp *.img ~/hikey/bin |
| 73 | > cp l-loader.bin ~/hikey.bin |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 74 | |
| 75 | These instructions are adapted from |
| 76 | https://github.com/96boards/documentation/wiki/HiKeyUEFI |
| 77 | |
| 78 | FLASHING |
| 79 | ======== |
| 80 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 81 | 1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 82 | the hisi-idt.py utility. |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 83 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 84 | The command below assumes HiKey enumerated as the first USB serial port |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 85 | > sudo ~/hikey/burn_boot/hisi-idt.py -d /dev/ttyUSB0 --img1=~/hikey/bin/l-loader.bin |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 86 | |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 87 | 2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device by plugging a USB A to mini B |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 88 | cable from your PC to the USB OTG port of HiKey (on some boards I've found this to be unreliable). |
| 89 | |
| 90 | > sudo fastboot devices |
| 91 | |
| 92 | 0123456789ABCDEF fastboot |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 93 | |
| 94 | 3. Flash the images |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 95 | |
| 96 | > sudo fastboot flash ptable ~/hikey/bin/ptable.img |
| 97 | > sudo fastboot flash fastboot ~/hikey/bin/fip.bin |
| 98 | > sudo fastboot flash nvme ~/hikey/bin/nvme.img |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 99 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 100 | 4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully) |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 101 | have ATF, booting u-boot from eMMC. On 'new' boards I've had to do the |
| 102 | flashing twice in the past to avoid an ATF error. |
| 103 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 104 | Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you |
| 105 | will get 'dwc_otg_core_host_init: Timeout!' errors. |
| 106 | |
Peter Griffin | 532d520 | 2016-04-20 17:14:03 +0100 | [diff] [blame] | 107 | See working boot trace below (by default trace is now output to UART3 not UART0 on latest |
| 108 | ATF, U-Boot and Kernel sources): - |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 109 | |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 110 | debug EMMC boot: send RST_N . |
| 111 | debug EMMC boot: start eMMC boot...... |
| 112 | load fastboot1! |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 113 | |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 114 | Switch to aarch64 mode. CPU0 executes at 0xf9801000! |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 115 | |
| 116 | INFO: BL1: 0xf9810000 - 0xf9817000 [size = 28672] |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 117 | NOTICE: Booting Trusted Firmware |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 118 | NOTICE: BL1: v1.1(debug):e8b7174 |
| 119 | NOTICE: BL1: Built : 19:16:44, Sep 8 2015 |
| 120 | INFO: BL1: RAM 0xf9810000 - 0xf9817000 |
| 121 | NOTICE: syspll frequency:1190494208Hz |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 122 | NOTICE: succeed to init lpddr3 rank0 dram phy |
| 123 | INFO: lpddr3_freq_init, set ddrc 533mhz |
| 124 | INFO: init ddr3 rank0 |
| 125 | INFO: ddr3 rank1 init pass |
| 126 | INFO: lpddr3_freq_init, set ddrc 800mhz |
| 127 | INFO: init ddr3 rank0 |
| 128 | INFO: ddr3 rank1 init pass |
| 129 | INFO: Elpida DDR |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 130 | INFO: ddr test value:0xa5a55a5a |
| 131 | INFO: Hisilicon HiKey platform is initialized |
| 132 | INFO: Using FIP |
| 133 | INFO: Loading file 'bl2.bin' at address 0xf9818000 |
| 134 | INFO: File 'bl2.bin' loaded: 0xf9818000 - 0xf9821100 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 135 | NOTICE: BL1: Booting BL2 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 136 | INFO: BL1: BL2 address = 0xf9818000 |
| 137 | INFO: BL1: BL2 spsr = 0x3c5 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 138 | INFO: [BDID] [fff91c18] midr: 0x410fd033 |
| 139 | INFO: [BDID] [fff91c1c] board type: 0 |
| 140 | INFO: [BDID] [fff91c20] board id: 0x2b |
| 141 | INFO: init_acpu_dvfs: pmic version 17 |
| 142 | INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00. |
| 143 | INFO: acpu_dvfs_volt_init: success! |
| 144 | INFO: acpu_dvfs_set_freq: support freq num is 5 |
| 145 | INFO: acpu_dvfs_set_freq: start prof is 0x4 |
| 146 | INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5 |
| 147 | INFO: acpu_dvfs_set_freq: voltage: |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 148 | INFO: - 0: 0x49 |
| 149 | INFO: - 1: 0x49 |
| 150 | INFO: - 2: 0x50 |
| 151 | INFO: - 3: 0x60 |
| 152 | INFO: - 4: 0x78 |
| 153 | NOTICE: acpu_dvfs_set_freq: set acpu freq success!NOTICE: BL2: v1.1(debug):e8b7174 |
| 154 | NOTICE: BL2: Built : 19:16:46, Sep 8 2015 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 155 | INFO: BL2: Loading BL3-0 |
| 156 | INFO: Using FIP |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 157 | INFO: Loading file 'bl30.bin' at address 0x1000000 |
| 158 | INFO: Skip reserving memory: 0x1000000 - 0x1023270 |
| 159 | INFO: File 'bl30.bin' loaded: 0x1000000 - 0x1023270 |
| 160 | INFO: bl2_plat_handle_bl30: [1000000] 3a334d43 34313032 2f38302f 30203133 |
| 161 | INFO: bl2_plat_handle_bl30: [10000c8] 0 0 b 0 |
| 162 | INFO: bl2_plat_handle_bl30: [1000190] 17 0 0 0 |
| 163 | INFO: bl2_plat_handle_bl30: [1023260] 0 0 0 0 |
| 164 | INFO: hisi_mcu_load_image: mcu sections 0: |
| 165 | INFO: hisi_mcu_load_image: src = 0x1000200 |
| 166 | INFO: hisi_mcu_load_image: dst = 0xf6000000 |
| 167 | INFO: hisi_mcu_load_image: size = 512 |
| 168 | INFO: hisi_mcu_load_image: [SRC 0x1000200] 0x7600 0x201 0x1eae1 0x1ea71 |
| 169 | INFO: hisi_mcu_load_image: [DST 0xf6000000] 0x7600 0x201 0x1eae1 0x1ea71 |
| 170 | INFO: hisi_mcu_load_image: mcu sections 1: |
| 171 | INFO: hisi_mcu_load_image: src = 0x1000400 |
| 172 | INFO: hisi_mcu_load_image: dst = 0xf6000200 |
| 173 | INFO: hisi_mcu_load_image: size = 27828 |
| 174 | INFO: hisi_mcu_load_image: [SRC 0x1000400] 0xbf00bf00 0x4815b672 0x48154780 0x60014915 |
| 175 | INFO: hisi_mcu_load_image: [DST 0xf6000200] 0xbf00bf00 0x4815b672 0x48154780 0x60014915 |
| 176 | INFO: hisi_mcu_load_image: mcu sections 2: |
| 177 | INFO: hisi_mcu_load_image: src = 0x10070b4 |
| 178 | INFO: hisi_mcu_load_image: dst = 0xf6007200 |
| 179 | INFO: hisi_mcu_load_image: size = 1024 |
| 180 | INFO: hisi_mcu_load_image: [SRC 0x10070b4] 0x55 0x0 0x0 0x0 |
| 181 | INFO: hisi_mcu_load_image: [DST 0xf6007200] 0x55 0x0 0x0 0x0 |
| 182 | INFO: hisi_mcu_load_image: mcu sections 3: |
| 183 | INFO: hisi_mcu_load_image: src = 0x10074b4 |
| 184 | INFO: hisi_mcu_load_image: dst = 0xfff8e000 |
| 185 | INFO: hisi_mcu_load_image: size = 12704 |
| 186 | INFO: hisi_mcu_load_image: [SRC 0x10074b4] 0x55 0x0 0x0 0x0 |
| 187 | INFO: hisi_mcu_load_image: [DST 0xfff8e000] 0x55 0x0 0x0 0x0 |
| 188 | INFO: hisi_mcu_load_image: mcu sections 4: |
| 189 | INFO: hisi_mcu_load_image: src = 0x100a654 |
| 190 | INFO: hisi_mcu_load_image: dst = 0x5e00000 |
| 191 | INFO: hisi_mcu_load_image: size = 82912 |
| 192 | INFO: hisi_mcu_load_image: [SRC 0x100a654] 0x4ff0e92d 0x2cc5f645 0x2600b0ab 0x2c7cf6c0 |
| 193 | INFO: hisi_mcu_load_image: [DST 0x5e00000] 0x4ff0e92d 0x2cc5f645 0x2600b0ab 0x2c7cf6c0 |
| 194 | INFO: hisi_mcu_load_image: mcu sections 5: |
| 195 | INFO: hisi_mcu_load_image: src = 0x101ea34 |
| 196 | INFO: hisi_mcu_load_image: dst = 0x5e143e0 |
| 197 | INFO: hisi_mcu_load_image: size = 12816 |
| 198 | INFO: hisi_mcu_load_image: [SRC 0x101ea34] 0x33323130 0x37363534 0x42413938 0x46454443 |
| 199 | INFO: hisi_mcu_load_image: [DST 0x5e143e0] 0x33323130 0x37363534 0x42413938 0x46454443 |
| 200 | INFO: hisi_mcu_load_image: mcu sections 6: |
| 201 | INFO: hisi_mcu_load_image: src = 0x1021c44 |
| 202 | INFO: hisi_mcu_load_image: dst = 0x5e1c1d0 |
| 203 | INFO: hisi_mcu_load_image: size = 3060 |
| 204 | INFO: hisi_mcu_load_image: [SRC 0x1021c44] 0x0 0x0 0x0 0x0 |
| 205 | INFO: hisi_mcu_load_image: [DST 0x5e1c1d0] 0x0 0x0 0x0 0x0 |
| 206 | INFO: hisi_mcu_load_image: mcu sections 7: |
| 207 | INFO: hisi_mcu_load_image: src = 0x1022838 |
| 208 | INFO: hisi_mcu_load_image: dst = 0x5e1cdc4 |
| 209 | INFO: hisi_mcu_load_image: size = 2616 |
| 210 | INFO: hisi_mcu_load_image: [SRC 0x1022838] 0xf80000a0 0x0 0xf80000ac 0x0 |
| 211 | INFO: hisi_mcu_load_image: [DST 0x5e1cdc4] 0xf80000a0 0x0 0xf80000ac 0x0 |
| 212 | INFO: hisi_mcu_start_run: AO_SC_SYS_CTRL2=0 |
| 213 | INFO: bl2_plat_handle_bl30: mcu pc is 42933301 |
| 214 | INFO: bl2_plat_handle_bl30: AO_SC_PERIPH_CLKSTAT4 is 39018f09 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 215 | INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000 |
| 216 | INFO: BL2: Loading BL3-1 |
| 217 | INFO: Using FIP |
| 218 | INFO: Loading file 'bl31.bin' at address 0xf9858000 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 219 | INFO: File 'bl31.bin' loaded: 0xf9858000 - 0xf9861010 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 220 | INFO: BL2: Loading BL3-2 |
| 221 | INFO: Using FIP |
| 222 | WARNING: Failed to access image 'bl32.bin' (-1) |
| 223 | WARNING: Failed to load BL3-2 (-1) |
| 224 | INFO: BL2: Loading BL3-3 |
| 225 | INFO: Using FIP |
| 226 | INFO: Loading file 'bl33.bin' at address 0x35000000 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 227 | INFO: File 'bl33.bin' loaded: 0x35000000 - 0x3504c468 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 228 | NOTICE: BL1: Booting BL3-1 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 229 | INFO: BL1: BL3-1 address = 0xf9858000 |
| 230 | INFO: BL1: BL3-1 spsr = 0x3cd |
| 231 | INFO: BL1: BL3-1 params address = 0xf9821920 |
| 232 | INFO: BL1: BL3-1 plat params address = 0x0 |
| 233 | NOTICE: BL3-1: v1.1(debug):e8b7174 |
| 234 | NOTICE: BL3-1: Built : 19:16:49, Sep 8 2015 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 235 | INFO: BL3-1: Initializing runtime services |
| 236 | INFO: BL3-1: Preparing for EL3 exit to normal world |
| 237 | INFO: BL3-1: Next image address = 0x35000000 |
| 238 | INFO: BL3-1: Next image spsr = 0x3c9 |
| 239 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 240 | U-Boot 2015.10-rc2 (Sep 08 2015 - 20:29:33 +0100)hikey |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 241 | |
| 242 | DRAM: 1008 MiB |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 243 | HI6553 PMIC init |
| 244 | MMC: config_sd_carddetect: SD card not present |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 245 | HiKey DWMMC: 0, HiKey DWMMC: 1 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 246 | Card did not respond to voltage select! |
| 247 | ** Bad device mmc 1 ** |
| 248 | Using default environment |
| 249 | |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 250 | In: serial |
| 251 | Out: serial |
| 252 | Err: serial |
| 253 | Net: Net Initialization Skipped |
| 254 | No ethernet found. |
| 255 | Hit any key to stop autoboot: 0 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame] | 256 | starting USB... |
| 257 | USB0: Core Release: 3.00a |
| 258 | scanning bus 0 for devices... 2 USB Device(s) found |
| 259 | scanning usb for storage devices... 0 Storage Device(s) found |
| 260 | scanning usb for ethernet devices... 0 Ethernet Device(s) found |