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gerrit.cesnet.cz / github / trini / u-boot / 20187fd11c37226fac8661bbac96ddd4fdf507b1 / . / arch / arm / dts / tegra30.dtsi
blob: 7be3791fc9a679536a1d63b1aac3fbb81c03eb31 [file] [log] [blame]
Simon Glass89460342014-06-11 23:29:52 -0600[diff] [blame]1#include <dt-bindings/gpio/tegra-gpio.h>
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3
Tom Warren6c5be642013-02-21 12:31:27 +0000[diff] [blame]4#include "skeleton.dtsi"
Tom Warren79ce91b2012-12-11 13:34:16 +0000[diff] [blame]5
6/ {
7 compatible = "nvidia,tegra30";
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]8
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]9 tegra_car: clock {
10 compatible = "nvidia,tegra30-car";
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]11 reg = <0x60006000 0x1000>;
12 #clock-cells = <1>;
13 };
14
Allen Martin64e6ec12013-01-11 23:07:04 +0000[diff] [blame]15 apbdma: dma {
16 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
17 reg = <0x6000a000 0x1400>;
18 interrupts = <0 104 0x04
19 0 105 0x04
20 0 106 0x04
21 0 107 0x04
22 0 108 0x04
23 0 109 0x04
24 0 110 0x04
25 0 111 0x04
26 0 112 0x04
27 0 113 0x04
28 0 114 0x04
29 0 115 0x04
30 0 116 0x04
31 0 117 0x04
32 0 118 0x04
33 0 119 0x04
34 0 128 0x04
35 0 129 0x04
36 0 130 0x04
37 0 131 0x04
38 0 132 0x04
39 0 133 0x04
40 0 134 0x04
41 0 135 0x04
42 0 136 0x04
43 0 137 0x04
44 0 138 0x04
45 0 139 0x04
46 0 140 0x04
47 0 141 0x04
48 0 142 0x04
49 0 143 0x04>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]50 clocks = <&tegra_car 34>;
51 };
52
Simon Glass89460342014-06-11 23:29:52 -0600[diff] [blame]53 gpio: gpio@6000d000 {
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]54 compatible = "nvidia,tegra30-gpio";
55 reg = <0x6000d000 0x1000>;
Simon Glass89460342014-06-11 23:29:52 -0600[diff] [blame]56 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
57 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]64 #gpio-cells = <2>;
65 gpio-controller;
66 #interrupt-cells = <2>;
67 interrupt-controller;
Allen Martin64e6ec12013-01-11 23:07:04 +0000[diff] [blame]68 };
69
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]70 i2c@7000c000 {
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]71 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
72 reg = <0x7000c000 0x100>;
73 interrupts = <0 38 0x04>;
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]74 #address-cells = <1>;
75 #size-cells = <0>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]76 clocks = <&tegra_car 12>, <&tegra_car 182>;
77 clock-names = "div-clk", "fast-clk";
78 status = "disabled";
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]79 };
80
81 i2c@7000c400 {
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]82 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
83 reg = <0x7000c400 0x100>;
84 interrupts = <0 84 0x04>;
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]85 #address-cells = <1>;
86 #size-cells = <0>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]87 clocks = <&tegra_car 54>, <&tegra_car 182>;
88 clock-names = "div-clk", "fast-clk";
89 status = "disabled";
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]90 };
91
92 i2c@7000c500 {
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]93 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
94 reg = <0x7000c500 0x100>;
95 interrupts = <0 92 0x04>;
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]96 #address-cells = <1>;
97 #size-cells = <0>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]98 clocks = <&tegra_car 67>, <&tegra_car 182>;
99 clock-names = "div-clk", "fast-clk";
100 status = "disabled";
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]101 };
102
103 i2c@7000c700 {
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]104 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
105 reg = <0x7000c700 0x100>;
106 interrupts = <0 120 0x04>;
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]107 #address-cells = <1>;
108 #size-cells = <0>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]109 clocks = <&tegra_car 103>, <&tegra_car 182>;
110 clock-names = "div-clk", "fast-clk";
111 status = "disabled";
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]112 };
113
114 i2c@7000d000 {
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]115 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
116 reg = <0x7000d000 0x100>;
117 interrupts = <0 53 0x04>;
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]118 #address-cells = <1>;
119 #size-cells = <0>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]120 clocks = <&tegra_car 47>, <&tegra_car 182>;
121 clock-names = "div-clk", "fast-clk";
122 status = "disabled";
Tom Warren083bbbb2012-12-21 15:59:15 -0700[diff] [blame]123 };
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]124
125 spi@7000d400 {
126 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
127 reg = <0x7000d400 0x200>;
128 interrupts = <0 59 0x04>;
129 nvidia,dma-request-selector = <&apbdma 15>;
130 #address-cells = <1>;
131 #size-cells = <0>;
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]132 clocks = <&tegra_car 41>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]133 status = "disabled";
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]134 };
135
136 spi@7000d600 {
137 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
138 reg = <0x7000d600 0x200>;
139 interrupts = <0 82 0x04>;
140 nvidia,dma-request-selector = <&apbdma 16>;
141 #address-cells = <1>;
142 #size-cells = <0>;
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]143 clocks = <&tegra_car 44>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]144 status = "disabled";
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]145 };
146
147 spi@7000d800 {
148 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
149 reg = <0x7000d480 0x200>;
150 interrupts = <0 83 0x04>;
151 nvidia,dma-request-selector = <&apbdma 17>;
152 #address-cells = <1>;
153 #size-cells = <0>;
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]154 clocks = <&tegra_car 46>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]155 status = "disabled";
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]156 };
157
158 spi@7000da00 {
159 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
160 reg = <0x7000da00 0x200>;
161 interrupts = <0 93 0x04>;
162 nvidia,dma-request-selector = <&apbdma 18>;
163 #address-cells = <1>;
164 #size-cells = <0>;
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]165 clocks = <&tegra_car 68>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]166 status = "disabled";
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]167 };
168
169 spi@7000dc00 {
170 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
171 reg = <0x7000dc00 0x200>;
172 interrupts = <0 94 0x04>;
173 nvidia,dma-request-selector = <&apbdma 27>;
174 #address-cells = <1>;
175 #size-cells = <0>;
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]176 clocks = <&tegra_car 104>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]177 status = "disabled";
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]178 };
179
180 spi@7000de00 {
181 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
182 reg = <0x7000de00 0x200>;
183 interrupts = <0 79 0x04>;
184 nvidia,dma-request-selector = <&apbdma 28>;
185 #address-cells = <1>;
186 #size-cells = <0>;
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]187 clocks = <&tegra_car 105>;
Tom Warren527519a2013-02-21 13:33:23 +0000[diff] [blame]188 status = "disabled";
Allen Martin23e31582013-01-29 13:51:26 +0000[diff] [blame]189 };
Tom Warren1baa4e72013-02-26 11:14:17 -0700[diff] [blame]190
191 sdhci@78000000 {
192 compatible = "nvidia,tegra30-sdhci";
193 reg = <0x78000000 0x200>;
194 interrupts = <0 14 0x04>;
195 clocks = <&tegra_car 14>;
196 status = "disabled";
197 };
198
199 sdhci@78000200 {
200 compatible = "nvidia,tegra30-sdhci";
201 reg = <0x78000200 0x200>;
202 interrupts = <0 15 0x04>;
203 clocks = <&tegra_car 9>;
204 status = "disabled";
205 };
206
207 sdhci@78000400 {
208 compatible = "nvidia,tegra30-sdhci";
209 reg = <0x78000400 0x200>;
210 interrupts = <0 19 0x04>;
211 clocks = <&tegra_car 69>;
212 status = "disabled";
213 };
214
215 sdhci@78000600 {
216 compatible = "nvidia,tegra30-sdhci";
217 reg = <0x78000600 0x200>;
218 interrupts = <0 31 0x04>;
219 clocks = <&tegra_car 15>;
220 status = "disabled";
221 };
Jim Lin56867d82013-06-21 19:05:46 +0800[diff] [blame]222
223 usb@7d000000 {
224 compatible = "nvidia,tegra30-ehci";
225 reg = <0x7d000000 0x4000>;
226 interrupts = <52>;
227 phy_type = "utmi";
228 clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
229 status = "disabled";
230 };
231
232 usb@7d004000 {
233 compatible = "nvidia,tegra30-ehci";
234 reg = <0x7d004000 0x4000>;
235 interrupts = <53>;
236 phy_type = "hsic";
237 clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
238 status = "disabled";
239 };
240
241 usb@7d008000 {
242 compatible = "nvidia,tegra30-ehci";
243 reg = <0x7d008000 0x4000>;
244 interrupts = <129>;
245 phy_type = "utmi";
246 clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
247 status = "disabled";
248 };
Tom Warren79ce91b2012-12-11 13:34:16 +0000[diff] [blame]249};