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wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk97d80fc2004-06-09 00:34:46 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/processor.h>
27#include <i2c.h>
28#include <spd.h>
29#include <asm/mmu.h>
30
Jon Loeligerd9b94f22005-07-25 14:05:07 -050031
32#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
33extern void dma_init(void);
wdenk9aea9532004-08-01 23:02:45 +000034extern uint dma_check(void);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050035extern int dma_xfer(void *dest, uint count, void *src);
wdenk42d1f032003-10-15 23:53:47 +000036#endif
37
wdenk384cc682005-04-03 22:35:21 +000038#ifdef CONFIG_SPD_EEPROM
wdenk42d1f032003-10-15 23:53:47 +000039
wdenk9aea9532004-08-01 23:02:45 +000040#ifndef CFG_READ_SPD
41#define CFG_READ_SPD i2c_read
42#endif
43
Jon Loeligerd9b94f22005-07-25 14:05:07 -050044static unsigned int setup_laws_and_tlbs(unsigned int memsize);
45
46
wdenk9aea9532004-08-01 23:02:45 +000047/*
48 * Convert picoseconds into clock cycles (rounding up if needed).
49 */
50
51int
52picos_to_clk(int picos)
53{
54 int clks;
55
56 clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
57 if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
58 clks++;
59 }
60
61 return clks;
62}
63
Jon Loeligerd9b94f22005-07-25 14:05:07 -050064
65/*
66 * Calculate the Density of each Physical Rank.
67 * Returned size is in bytes.
68 *
69 * Study these table from Byte 31 of JEDEC SPD Spec.
70 *
71 * DDR I DDR II
72 * Bit Size Size
73 * --- ----- ------
74 * 7 high 512MB 512MB
75 * 6 256MB 256MB
76 * 5 128MB 128MB
77 * 4 64MB 16GB
78 * 3 32MB 8GB
79 * 2 16MB 4GB
80 * 1 2GB 2GB
81 * 0 low 1GB 1GB
82 *
83 * Reorder Table to be linear by stripping the bottom
84 * 2 or 5 bits off and shifting them up to the top.
85 */
86
wdenk9aea9532004-08-01 23:02:45 +000087unsigned int
Jon Loeligerd9b94f22005-07-25 14:05:07 -050088compute_banksize(unsigned int mem_type, unsigned char row_dens)
wdenk9aea9532004-08-01 23:02:45 +000089{
Jon Loeligerd9b94f22005-07-25 14:05:07 -050090 unsigned int bsize;
91
92 if (mem_type == SPD_MEMTYPE_DDR) {
93 /* Bottom 2 bits up to the top. */
94 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
95 debug("DDR: DDR I rank density = 0x%08x\n", bsize);
96 } else {
97 /* Bottom 5 bits up to the top. */
98 bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
99 debug("DDR: DDR II rank density = 0x%08x\n", bsize);
100 }
101 return bsize;
wdenk9aea9532004-08-01 23:02:45 +0000102}
103
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500104
105/*
106 * Convert a two-nibble BCD value into a cycle time.
107 * While the spec calls for nano-seconds, picos are returned.
108 *
109 * This implements the tables for bytes 9, 23 and 25 for both
110 * DDR I and II. No allowance for distinguishing the invalid
111 * fields absent for DDR I yet present in DDR II is made.
112 * (That is, cycle times of .25, .33, .66 and .75 ns are
113 * allowed for both DDR II and I.)
114 */
115
116unsigned int
117convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
118{
119 /*
120 * Table look up the lower nibble, allow DDR I & II.
121 */
122 unsigned int tenths_ps[16] = {
123 0,
124 100,
125 200,
126 300,
127 400,
128 500,
129 600,
130 700,
131 800,
132 900,
133 250,
Jon Loeliger1fd56992006-10-10 17:19:03 -0500134 330,
135 660,
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500136 750,
137 0, /* undefined */
138 0 /* undefined */
139 };
140
141 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
142 unsigned int tenth_ns = spd_val & 0x0F;
143 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
144
145 return ps;
146}
147
148
Jon Loeliger1fd56992006-10-10 17:19:03 -0500149/*
150 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
151 * Table from SPD Spec, Byte 12, converted to picoseconds and
152 * filled in with "default" normal values.
153 */
154unsigned int determine_refresh_rate(unsigned int spd_refresh)
155{
156 unsigned int refresh_time_ns[8] = {
157 15625000, /* 0 Normal 1.00x */
158 3900000, /* 1 Reduced .25x */
159 7800000, /* 2 Extended .50x */
160 31300000, /* 3 Extended 2.00x */
161 62500000, /* 4 Extended 4.00x */
162 125000000, /* 5 Extended 8.00x */
163 15625000, /* 6 Normal 1.00x filler */
164 15625000, /* 7 Normal 1.00x filler */
165 };
166
167 return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
168}
169
170
wdenk9aea9532004-08-01 23:02:45 +0000171long int
172spd_sdram(void)
173{
174 volatile immap_t *immap = (immap_t *)CFG_IMMR;
175 volatile ccsr_ddr_t *ddr = &immap->im_ddr;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500176 volatile ccsr_gur_t *gur = &immap->im_gur;
wdenk9aea9532004-08-01 23:02:45 +0000177 spd_eeprom_t spd;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500178 unsigned int n_ranks;
179 unsigned int rank_density;
180 unsigned int odt_rd_cfg, odt_wr_cfg;
181 unsigned int odt_cfg, mode_odt_enable;
Jon Loeliger1fd56992006-10-10 17:19:03 -0500182 unsigned int refresh_clk;
183#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
184 unsigned char clk_adjust;
185#endif
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500186 unsigned int dqs_cfg;
187 unsigned char twr_clk, twtr_clk, twr_auto_clk;
188 unsigned int tCKmin_ps, tCKmax_ps;
189 unsigned int max_data_rate, effective_data_rate;
190 unsigned int busfreq;
191 unsigned sdram_cfg;
wdenk9aea9532004-08-01 23:02:45 +0000192 unsigned int memsize;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500193 unsigned char caslat, caslat_ctrl;
194 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
195 unsigned int trcd_clk;
196 unsigned int trtp_clk;
197 unsigned char cke_min_clk;
198 unsigned char add_lat;
199 unsigned char wr_lat;
200 unsigned char wr_data_delay;
201 unsigned char four_act;
202 unsigned char cpo;
203 unsigned char burst_len;
204 unsigned int mode_caslat;
205 unsigned char sdram_type;
206 unsigned char d_init;
wdenk9aea9532004-08-01 23:02:45 +0000207
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500208 /*
209 * Read SPD information.
210 */
211 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd));
wdenk9aea9532004-08-01 23:02:45 +0000212
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500213 /*
214 * Check for supported memory module types.
215 */
216 if (spd.mem_type != SPD_MEMTYPE_DDR &&
217 spd.mem_type != SPD_MEMTYPE_DDR2) {
218 printf("Unable to locate DDR I or DDR II module.\n"
219 " Fundamental memory type is 0x%0x\n",
220 spd.mem_type);
wdenk9aea9532004-08-01 23:02:45 +0000221 return 0;
222 }
223
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500224 /*
225 * These test gloss over DDR I and II differences in interpretation
226 * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
227 * are not supported on DDR I; and not encoded on DDR II.
228 *
229 * Also note that the 8548 controller can support:
230 * 12 <= nrow <= 16
231 * and
232 * 8 <= ncol <= 11 (still, for DDR)
233 * 6 <= ncol <= 9 (for FCRAM)
234 */
235 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
236 printf("DDR: Unsupported number of Row Addr lines: %d.\n",
237 spd.nrow_addr);
238 return 0;
239 }
240 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
241 printf("DDR: Unsupported number of Column Addr lines: %d.\n",
242 spd.ncol_addr);
wdenk9aea9532004-08-01 23:02:45 +0000243 return 0;
244 }
245
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500246 /*
247 * Determine the number of physical banks controlled by
248 * different Chip Select signals. This is not quite the
249 * same as the number of DIMM modules on the board. Feh.
250 */
251 if (spd.mem_type == SPD_MEMTYPE_DDR) {
252 n_ranks = spd.nrows;
253 } else {
254 n_ranks = (spd.nrows & 0x7) + 1;
255 }
256
257 debug("DDR: number of ranks = %d\n", n_ranks);
258
259 if (n_ranks > 2) {
260 printf("DDR: Only 2 chip selects are supported: %d\n",
261 n_ranks);
262 return 0;
263 }
264
265 /*
Andy Fleming1f9a3182007-02-23 16:28:46 -0600266 * Adjust DDR II IO voltage biasing.
267 * Only 8548 rev 1 needs the fix
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500268 */
Andy Fleming1f9a3182007-02-23 16:28:46 -0600269 if ((SVR_VER(get_svr()) == SVR_8548_E) &&
270 (SVR_MJREV(get_svr()) == 1) &&
271 (spd.mem_type == SPD_MEMTYPE_DDR2)) {
272 gur->ddrioovcr = (0x80000000 /* Enable */
273 | 0x10000000);/* VSEL to 1.8V */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500274 }
275
276 /*
277 * Determine the size of each Rank in bytes.
278 */
279 rank_density = compute_banksize(spd.mem_type, spd.row_dens);
280
281
282 /*
283 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
284 */
285 ddr->cs0_bnds = (rank_density >> 24) - 1;
286
287 /*
288 * ODT configuration recommendation from DDR Controller Chapter.
289 */
290 odt_rd_cfg = 0; /* Never assert ODT */
291 odt_wr_cfg = 0; /* Never assert ODT */
292 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
293 odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
294#if 0
295 /* FIXME: How to determine the number of dimm modules? */
296 if (n_dimm_modules == 2) {
297 odt_rd_cfg = 1; /* Assert ODT on reads to CS0 */
298 }
299#endif
300 }
301
wdenk9aea9532004-08-01 23:02:45 +0000302 ddr->cs0_config = ( 1 << 31
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500303 | (odt_rd_cfg << 20)
304 | (odt_wr_cfg << 16)
wdenk9aea9532004-08-01 23:02:45 +0000305 | (spd.nrow_addr - 12) << 8
306 | (spd.ncol_addr - 8) );
307 debug("\n");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500308 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
309 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
wdenk9aea9532004-08-01 23:02:45 +0000310
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500311 if (n_ranks == 2) {
312 /*
313 * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg
314 */
315 ddr->cs1_bnds = ( (rank_density >> 8)
316 | ((rank_density >> (24 - 1)) - 1) );
wdenk9aea9532004-08-01 23:02:45 +0000317 ddr->cs1_config = ( 1<<31
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500318 | (odt_rd_cfg << 20)
319 | (odt_wr_cfg << 16)
320 | (spd.nrow_addr - 12) << 8
321 | (spd.ncol_addr - 8) );
322 debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
323 debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
wdenk9aea9532004-08-01 23:02:45 +0000324 }
325
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500326
327 /*
328 * Find the largest CAS by locating the highest 1 bit
329 * in the spd.cas_lat field. Translate it to a DDR
330 * controller field value:
331 *
332 * CAS Lat DDR I DDR II Ctrl
333 * Clocks SPD Bit SPD Bit Value
334 * ------- ------- ------- -----
335 * 1.0 0 0001
336 * 1.5 1 0010
337 * 2.0 2 2 0011
338 * 2.5 3 0100
339 * 3.0 4 3 0101
340 * 3.5 5 0110
341 * 4.0 4 0111
342 * 4.5 1000
343 * 5.0 5 1001
344 */
345 caslat = __ilog2(spd.cas_lat);
346 if ((spd.mem_type == SPD_MEMTYPE_DDR)
347 && (caslat > 5)) {
348 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
349 return 0;
350
351 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
352 && (caslat < 2 || caslat > 5)) {
353 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
354 spd.cas_lat);
wdenk9aea9532004-08-01 23:02:45 +0000355 return 0;
356 }
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500357 debug("DDR: caslat SPD bit is %d\n", caslat);
358
359 /*
360 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
361 * The SPD clk_cycle field (tCKmin) is measured in tenths of
362 * nanoseconds and represented as BCD.
363 */
364 tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
365 debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
366
367 /*
368 * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
369 */
370 max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
371 debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
372
373
374 /*
375 * Adjust the CAS Latency to allow for bus speeds that
376 * are slower than the DDR module.
377 */
378 busfreq = get_bus_freq(0) / 1000000; /* MHz */
379
380 effective_data_rate = max_data_rate;
381 if (busfreq < 90) {
382 /* DDR rate out-of-range */
383 puts("DDR: platform frequency is not fit for DDR rate\n");
384 return 0;
385
386 } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
387 /*
388 * busfreq 90~230 range, treated as DDR 200.
389 */
390 effective_data_rate = 200;
391 if (spd.clk_cycle3 == 0xa0) /* 10 ns */
392 caslat -= 2;
393 else if (spd.clk_cycle2 == 0xa0)
394 caslat--;
395
396 } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
397 /*
398 * busfreq 230~280 range, treated as DDR 266.
399 */
400 effective_data_rate = 266;
401 if (spd.clk_cycle3 == 0x75) /* 7.5 ns */
402 caslat -= 2;
403 else if (spd.clk_cycle2 == 0x75)
404 caslat--;
405
406 } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
407 /*
408 * busfreq 280~350 range, treated as DDR 333.
409 */
410 effective_data_rate = 333;
411 if (spd.clk_cycle3 == 0x60) /* 6.0 ns */
412 caslat -= 2;
413 else if (spd.clk_cycle2 == 0x60)
414 caslat--;
415
416 } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
417 /*
418 * busfreq 350~460 range, treated as DDR 400.
419 */
420 effective_data_rate = 400;
421 if (spd.clk_cycle3 == 0x50) /* 5.0 ns */
422 caslat -= 2;
423 else if (spd.clk_cycle2 == 0x50)
424 caslat--;
425
426 } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
427 /*
428 * busfreq 460~560 range, treated as DDR 533.
429 */
430 effective_data_rate = 533;
431 if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */
432 caslat -= 2;
433 else if (spd.clk_cycle2 == 0x3D)
434 caslat--;
435
436 } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
437 /*
438 * busfreq 560~700 range, treated as DDR 667.
439 */
440 effective_data_rate = 667;
441 if (spd.clk_cycle3 == 0x30) /* 3.0 ns */
442 caslat -= 2;
443 else if (spd.clk_cycle2 == 0x30)
444 caslat--;
445
446 } else if (700 <= busfreq) {
447 /*
448 * DDR rate out-of-range
449 */
450 printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
451 busfreq, max_data_rate);
452 return 0;
453 }
454
455
456 /*
457 * Convert caslat clocks to DDR controller value.
458 * Force caslat_ctrl to be DDR Controller field-sized.
459 */
460 if (spd.mem_type == SPD_MEMTYPE_DDR) {
461 caslat_ctrl = (caslat + 1) & 0x07;
462 } else {
463 caslat_ctrl = (2 * caslat - 1) & 0x0f;
464 }
465
466 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
467 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
468 caslat, caslat_ctrl);
469
470 /*
471 * Timing Config 0.
472 * Avoid writing for DDR I. The new PQ38 DDR controller
473 * dreams up non-zero default values to be backwards compatible.
474 */
475 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
476 unsigned char taxpd_clk = 8; /* By the book. */
477 unsigned char tmrd_clk = 2; /* By the book. */
478 unsigned char act_pd_exit = 2; /* Empirical? */
479 unsigned char pre_pd_exit = 6; /* Empirical? */
480
481 ddr->timing_cfg_0 = (0
482 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
483 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
484 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
485 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
486 );
487#if 0
488 ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
489#endif
490 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
491
492 } else {
493#if 0
494 /*
495 * Force extra cycles with 0xaa bits.
496 * Incidentally supply the dreamt-up backwards compat value!
497 */
498 ddr->timing_cfg_0 = 0x00110105; /* backwards compat value */
499 ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
500 debug("DDR: HACK timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
501#endif
502 }
503
504
505 /*
506 * Some Timing Config 1 values now.
507 * Sneak Extended Refresh Recovery in here too.
508 */
509
510 /*
511 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
512 * use conservative value.
513 * For DDR II, they are bytes 36 and 37, in quarter nanos.
514 */
515
516 if (spd.mem_type == SPD_MEMTYPE_DDR) {
517 twr_clk = 3; /* Clocks */
518 twtr_clk = 1; /* Clocks */
519 } else {
520 twr_clk = picos_to_clk(spd.twr * 250);
521 twtr_clk = picos_to_clk(spd.twtr * 250);
522 }
523
524 /*
525 * Calculate Trfc, in picos.
526 * DDR I: Byte 42 straight up in ns.
527 * DDR II: Byte 40 and 42 swizzled some, in ns.
528 */
529 if (spd.mem_type == SPD_MEMTYPE_DDR) {
530 trfc = spd.trfc * 1000; /* up to ps */
531 } else {
532 unsigned int byte40_table_ps[8] = {
533 0,
534 250,
535 330,
536 500,
537 660,
538 750,
539 0,
540 0
541 };
542
543 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
544 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
545 }
546 trfc_clk = picos_to_clk(trfc);
547
548 /*
549 * Trcd, Byte 29, from quarter nanos to ps and clocks.
550 */
551 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
552
553 /*
554 * Convert trfc_clk to DDR controller fields. DDR I should
555 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
556 * 8548 controller has an extended REFREC field of three bits.
557 * The controller automatically adds 8 clocks to this value,
558 * so preadjust it down 8 first before splitting it up.
559 */
560 trfc_low = (trfc_clk - 8) & 0xf;
561 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
562
563 /*
564 * Sneak in some Extended Refresh Recovery.
565 */
566 ddr->ext_refrec = (trfc_high << 16);
567 debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
568
569 ddr->timing_cfg_1 =
570 (0
571 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
572 | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
573 | (trcd_clk << 20) /* ACTTORW */
574 | (caslat_ctrl << 16) /* CASLAT */
575 | (trfc_low << 12) /* REFEC */
576 | ((twr_clk & 0x07) << 8) /* WRRREC */
577 | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
578 | ((twtr_clk & 0x07) << 0) /* WRTORD */
579 );
580
581 debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
582
583
584 /*
585 * Timing_Config_2
586 * Was: 0x00000800;
587 */
588
589 /*
590 * Additive Latency
591 * For DDR I, 0.
592 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
593 * which comes from Trcd, and also note that:
594 * add_lat + caslat must be >= 4
595 */
596 add_lat = 0;
597 if (spd.mem_type == SPD_MEMTYPE_DDR2
598 && (odt_wr_cfg || odt_rd_cfg)
599 && (caslat < 4)) {
600 add_lat = 4 - caslat;
601 if (add_lat > trcd_clk) {
602 add_lat = trcd_clk - 1;
603 }
604 }
605
606 /*
607 * Write Data Delay
608 * Historically 0x2 == 4/8 clock delay.
609 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
610 */
611 wr_data_delay = 3;
612
613 /*
614 * Write Latency
615 * Read to Precharge
616 * Minimum CKE Pulse Width.
617 * Four Activate Window
618 */
619 if (spd.mem_type == SPD_MEMTYPE_DDR) {
620 /*
621 * This is a lie. It should really be 1, but if it is
622 * set to 1, bits overlap into the old controller's
623 * otherwise unused ACSM field. If we leave it 0, then
624 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
625 */
626 wr_lat = 0;
627
628 trtp_clk = 2; /* By the book. */
629 cke_min_clk = 1; /* By the book. */
630 four_act = 1; /* By the book. */
631
632 } else {
633 wr_lat = caslat - 1;
634
635 /* Convert SPD value from quarter nanos to picos. */
636 trtp_clk = picos_to_clk(spd.trtp * 250);
637
638 cke_min_clk = 3; /* By the book. */
639 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
640 }
641
642 /*
643 * Empirically set ~MCAS-to-preamble override for DDR 2.
644 * Your milage will vary.
645 */
646 cpo = 0;
647 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
648 if (effective_data_rate == 266 || effective_data_rate == 333) {
649 cpo = 0x7; /* READ_LAT + 5/4 */
650 } else if (effective_data_rate == 400) {
651 cpo = 0x9; /* READ_LAT + 7/4 */
652 } else {
653 /* Pure speculation */
654 cpo = 0xb;
655 }
656 }
657
658 ddr->timing_cfg_2 = (0
659 | ((add_lat & 0x7) << 28) /* ADD_LAT */
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500660 | ((cpo & 0x1f) << 23) /* CPO */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500661 | ((wr_lat & 0x7) << 19) /* WR_LAT */
662 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
663 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
664 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
665 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
666 );
667
668 debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
669
670
671 /*
672 * Determine the Mode Register Set.
673 *
674 * This is nominally part specific, but it appears to be
675 * consistent for all DDR I devices, and for all DDR II devices.
676 *
677 * caslat must be programmed
678 * burst length is always 4
679 * burst type is sequential
680 *
681 * For DDR I:
682 * operating mode is "normal"
683 *
684 * For DDR II:
685 * other stuff
686 */
687
688 mode_caslat = 0;
689
690 /*
691 * Table lookup from DDR I or II Device Operation Specs.
692 */
693 if (spd.mem_type == SPD_MEMTYPE_DDR) {
694 if (1 <= caslat && caslat <= 4) {
695 unsigned char mode_caslat_table[4] = {
696 0x5, /* 1.5 clocks */
697 0x2, /* 2.0 clocks */
698 0x6, /* 2.5 clocks */
699 0x3 /* 3.0 clocks */
700 };
701 mode_caslat = mode_caslat_table[caslat - 1];
702 } else {
703 puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
704 "2.5 and 3.0 clocks are supported.\n");
705 return 0;
706 }
707
708 } else {
709 if (2 <= caslat && caslat <= 5) {
710 mode_caslat = caslat;
711 } else {
712 puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
713 "4.0 and 5.0 clocks are supported.\n");
714 return 0;
715 }
716 }
717
718 /*
719 * Encoded Burst Lenght of 4.
720 */
721 burst_len = 2; /* Fiat. */
722
723 if (spd.mem_type == SPD_MEMTYPE_DDR) {
724 twr_auto_clk = 0; /* Historical */
725 } else {
726 /*
727 * Determine tCK max in picos. Grab tWR and convert to picos.
728 * Auto-precharge write recovery is:
729 * WR = roundup(tWR_ns/tCKmax_ns).
730 *
731 * Ponder: Is twr_auto_clk different than twr_clk?
732 */
733 tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
734 twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
735 }
736
737
738 /*
739 * Mode Reg in bits 16 ~ 31,
740 * Extended Mode Reg 1 in bits 0 ~ 15.
741 */
742 mode_odt_enable = 0x0; /* Default disabled */
743 if (odt_wr_cfg || odt_rd_cfg) {
744 /*
745 * Bits 6 and 2 in Extended MRS(1)
746 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
747 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
748 */
749 mode_odt_enable = 0x40; /* 150 Ohm */
750 }
751
752 ddr->sdram_mode =
753 (0
754 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
755 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
756 | (twr_auto_clk << 9) /* Write Recovery Autopre */
757 | (mode_caslat << 4) /* caslat */
758 | (burst_len << 0) /* Burst length */
759 );
760
761 debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode);
762
763
764 /*
765 * Clear EMRS2 and EMRS3.
766 */
767 ddr->sdram_mode_2 = 0;
768 debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
769
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500770 /*
Jon Loeliger1fd56992006-10-10 17:19:03 -0500771 * Determine Refresh Rate.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500772 */
Jon Loeliger1fd56992006-10-10 17:19:03 -0500773 refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
Wolfgang Denk47a69892006-10-24 15:32:57 +0200774
Jon Loeliger1fd56992006-10-10 17:19:03 -0500775 /*
776 * Set BSTOPRE to 0x100 for page mode
777 * If auto-charge is used, set BSTOPRE = 0
778 */
779 ddr->sdram_interval =
780 (0
781 | (refresh_clk & 0x3fff) << 16
782 | 0x100
783 );
784 debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500785
786 /*
787 * Is this an ECC DDR chip?
788 * But don't mess with it if the DDR controller will init mem.
789 */
Andy Fleming9343dbf2007-02-24 01:16:45 -0600790#ifdef CONFIG_DDR_ECC
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500791 if (spd.config == 0x02) {
Andy Fleming9343dbf2007-02-24 01:16:45 -0600792#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500793 ddr->err_disable = 0x0000000d;
Andy Fleming9343dbf2007-02-24 01:16:45 -0600794#endif
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500795 ddr->err_sbe = 0x00ff0000;
796 }
Andy Fleming9343dbf2007-02-24 01:16:45 -0600797
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500798 debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
799 debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
Andy Fleming9343dbf2007-02-24 01:16:45 -0600800#endif /* CONFIG_DDR_ECC */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500801
802 asm("sync;isync;msync");
803 udelay(500);
804
805 /*
806 * SDRAM Cfg 2
807 */
808
809 /*
810 * When ODT is enabled, Chap 9 suggests asserting ODT to
811 * internal IOs only during reads.
812 */
813 odt_cfg = 0;
814 if (odt_rd_cfg | odt_wr_cfg) {
815 odt_cfg = 0x2; /* ODT to IOs during reads */
816 }
817
818 /*
819 * Try to use differential DQS with DDR II.
820 */
821 if (spd.mem_type == SPD_MEMTYPE_DDR) {
822 dqs_cfg = 0; /* No Differential DQS for DDR I */
823 } else {
824 dqs_cfg = 0x1; /* Differential DQS for DDR II */
825 }
826
827#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
828 /*
829 * Use the DDR controller to auto initialize memory.
830 */
831 d_init = 1;
832 ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
833 debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
834#else
835 /*
836 * Memory will be initialized via DMA, or not at all.
837 */
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500838 d_init = 0;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500839#endif
840
841 ddr->sdram_cfg_2 = (0
842 | (dqs_cfg << 26) /* Differential DQS */
843 | (odt_cfg << 21) /* ODT */
844 | (d_init << 4) /* D_INIT auto init DDR */
845 );
846
847 debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
848
849
850#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
Jon Loeliger1fd56992006-10-10 17:19:03 -0500851 /*
852 * Setup the clock control.
853 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
854 * SDRAM_CLK_CNTL[5-7] = Clock Adjust
855 * 0110 3/4 cycle late
856 * 0111 7/8 cycle late
857 */
858 if (spd.mem_type == SPD_MEMTYPE_DDR)
859 clk_adjust = 0x6;
860 else
861 clk_adjust = 0x7;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500862
Jon Loeliger1fd56992006-10-10 17:19:03 -0500863 ddr->sdram_clk_cntl = (0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500864 | 0x80000000
865 | (clk_adjust << 23)
866 );
Jon Loeliger1fd56992006-10-10 17:19:03 -0500867 debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500868#endif
869
870 /*
871 * Figure out the settings for the sdram_cfg register.
872 * Build up the entire register in 'sdram_cfg' before writing
873 * since the write into the register will actually enable the
874 * memory controller; all settings must be done before enabling.
875 *
876 * sdram_cfg[0] = 1 (ddr sdram logic enable)
877 * sdram_cfg[1] = 1 (self-refresh-enable)
878 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
879 * 010 DDR 1 SDRAM
880 * 011 DDR 2 SDRAM
881 */
882 sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
883 sdram_cfg = (0
884 | (1 << 31) /* Enable */
885 | (1 << 30) /* Self refresh */
886 | (sdram_type << 24) /* SDRAM type */
887 );
888
889 /*
890 * sdram_cfg[3] = RD_EN - registered DIMM enable
891 * A value of 0x26 indicates micron registered DIMMS (micron.com)
892 */
893 if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) {
894 sdram_cfg |= 0x10000000; /* RD_EN */
895 }
896
897#if defined(CONFIG_DDR_ECC)
898 /*
899 * If the user wanted ECC (enabled via sdram_cfg[2])
900 */
901 if (spd.config == 0x02) {
902 sdram_cfg |= 0x20000000; /* ECC_EN */
903 }
904#endif
905
906 /*
907 * REV1 uses 1T timing.
908 * REV2 may use 1T or 2T as configured by the user.
909 */
910 {
911 uint pvr = get_pvr();
912
913 if (pvr != PVR_85xx_REV1) {
914#if defined(CONFIG_DDR_2T_TIMING)
915 /*
916 * Enable 2T timing by setting sdram_cfg[16].
917 */
918 sdram_cfg |= 0x8000; /* 2T_EN */
919#endif
920 }
921 }
922
923 /*
924 * 200 painful micro-seconds must elapse between
925 * the DDR clock setup and the DDR config enable.
926 */
927 udelay(200);
928
929 /*
930 * Go!
931 */
932 ddr->sdram_cfg = sdram_cfg;
933
934 asm("sync;isync;msync");
935 udelay(500);
936
937 debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg);
938
939
940#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
941 /*
942 * Poll until memory is initialized.
943 * 512 Meg at 400 might hit this 200 times or so.
944 */
945 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
946 udelay(1000);
947 }
948#endif
949
wdenk9aea9532004-08-01 23:02:45 +0000950
951 /*
952 * Figure out memory size in Megabytes.
953 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500954 memsize = n_ranks * rank_density / 0x100000;
wdenk9aea9532004-08-01 23:02:45 +0000955
956 /*
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500957 * Establish Local Access Window and TLB mappings for DDR memory.
wdenk9aea9532004-08-01 23:02:45 +0000958 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500959 memsize = setup_laws_and_tlbs(memsize);
960 if (memsize == 0) {
961 return 0;
962 }
963
964 return memsize * 1024 * 1024;
965}
966
967
968/*
969 * Setup Local Access Window and TLB1 mappings for the requested
970 * amount of memory. Returns the amount of memory actually mapped
971 * (usually the original request size), or 0 on error.
972 */
973
974static unsigned int
975setup_laws_and_tlbs(unsigned int memsize)
976{
977 volatile immap_t *immap = (immap_t *)CFG_IMMR;
978 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
979 unsigned int tlb_size;
980 unsigned int law_size;
981 unsigned int ram_tlb_index;
982 unsigned int ram_tlb_address;
wdenk9aea9532004-08-01 23:02:45 +0000983
984 /*
985 * Determine size of each TLB1 entry.
986 */
987 switch (memsize) {
988 case 16:
989 case 32:
990 tlb_size = BOOKE_PAGESZ_16M;
991 break;
992 case 64:
993 case 128:
994 tlb_size = BOOKE_PAGESZ_64M;
995 break;
996 case 256:
997 case 512:
998 case 1024:
999 case 2048:
1000 tlb_size = BOOKE_PAGESZ_256M;
1001 break;
1002 default:
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001003 puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
1004
1005 /*
1006 * The memory was not able to be mapped.
1007 */
wdenk9aea9532004-08-01 23:02:45 +00001008 return 0;
1009 break;
1010 }
1011
1012 /*
1013 * Configure DDR TLB1 entries.
1014 * Starting at TLB1 8, use no more than 8 TLB1 entries.
1015 */
1016 ram_tlb_index = 8;
1017 ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
1018 while (ram_tlb_address < (memsize * 1024 * 1024)
1019 && ram_tlb_index < 16) {
1020 mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
1021 mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
1022 mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
1023 0, 0, 0, 0, 0, 0, 0, 0));
1024 mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
1025 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
1026 asm volatile("isync;msync;tlbwe;isync");
1027
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001028 debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
1029 debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
1030 debug("DDR: MAS2=0x%08x\n",
wdenk9aea9532004-08-01 23:02:45 +00001031 TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
1032 0, 0, 0, 0, 0, 0, 0, 0));
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001033 debug("DDR: MAS3=0x%08x\n",
wdenk9aea9532004-08-01 23:02:45 +00001034 TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
1035 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
1036
1037 ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
1038 ram_tlb_index++;
1039 }
1040
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001041
1042 /*
1043 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
1044 */
1045 law_size = 19 + __ilog2(memsize);
1046
wdenk9aea9532004-08-01 23:02:45 +00001047 /*
1048 * Set up LAWBAR for all of DDR.
1049 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001050 ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1051 ecm->lawar1 = (LAWAR_EN
1052 | LAWAR_TRGT_IF_DDR
1053 | (LAWAR_SIZE & law_size));
1054 debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1);
1055 debug("DDR: LARAR1=0x%08x\n", ecm->lawar1);
wdenk9aea9532004-08-01 23:02:45 +00001056
1057 /*
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001058 * Confirm that the requested amount of memory was mapped.
wdenk9aea9532004-08-01 23:02:45 +00001059 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001060 return memsize;
wdenk42d1f032003-10-15 23:53:47 +00001061}
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001062
wdenk42d1f032003-10-15 23:53:47 +00001063#endif /* CONFIG_SPD_EEPROM */
wdenk9aea9532004-08-01 23:02:45 +00001064
1065
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001066#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1067
wdenk9aea9532004-08-01 23:02:45 +00001068/*
1069 * Initialize all of memory for ECC, then enable errors.
1070 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001071
wdenk9aea9532004-08-01 23:02:45 +00001072void
1073ddr_enable_ecc(unsigned int dram_size)
1074{
1075 uint *p = 0;
1076 uint i = 0;
1077 volatile immap_t *immap = (immap_t *)CFG_IMMR;
1078 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
1079
1080 dma_init();
1081
1082 for (*p = 0; p < (uint *)(8 * 1024); p++) {
1083 if (((unsigned int)p & 0x1f) == 0) {
1084 ppcDcbz((unsigned long) p);
1085 }
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001086 *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
wdenk9aea9532004-08-01 23:02:45 +00001087 if (((unsigned int)p & 0x1c) == 0x1c) {
1088 ppcDcbf((unsigned long) p);
1089 }
1090 }
1091
Jon Loeliger1fd56992006-10-10 17:19:03 -05001092 dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
1093 dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
1094 dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
1095 dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
1096 dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
1097 dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
1098 dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
1099 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
1100 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
1101 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
wdenk9aea9532004-08-01 23:02:45 +00001102
1103 for (i = 1; i < dram_size / 0x800000; i++) {
1104 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
1105 }
1106
1107 /*
1108 * Enable errors for ECC.
1109 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001110 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
wdenk9aea9532004-08-01 23:02:45 +00001111 ddr->err_disable = 0x00000000;
1112 asm("sync;isync;msync");
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001113 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
wdenk9aea9532004-08-01 23:02:45 +00001114}
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001115
1116#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */