blob: f5883c02ddd317d2917b44281ccf4830b2432803 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +01002/*
Hannes Schmelzere880a5e2018-01-09 19:01:32 +01003 * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
4 * B&R Industrial Automation GmbH - http://www.br-automation.com
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +01005 */
6
7#ifndef AM335X_FB_H
8#define AM335X_FB_H
9
10#define HSVS_CONTROL (0x01 << 25) /*
11 * 0 = lcd_lp and lcd_fp are driven on
12 * opposite edges of pixel clock than
13 * the lcd_pixel_o
14 * 1 = lcd_lp and lcd_fp are driven
15 * according to bit 24 Note that this
16 * bit MUST be set to '0' for Passive
17 * Matrix displays the edge timing is
18 * fixed
19 */
20#define HSVS_RISEFALL (0x01 << 24) /*
21 * 0 = lcd_lp and lcd_fp are driven on
22 * the rising edge of pixel clock (bit
23 * 25 must be set to 1)
24 * 1 = lcd_lp and lcd_fp are driven on
25 * the falling edge of pixel clock (bit
26 * 25 must be set to 1)
27 */
28#define DE_INVERT (0x01 << 23) /*
29 * 0 = DE is low-active
30 * 1 = DE is high-active
31 */
32#define PXCLK_INVERT (0x01 << 22) /*
33 * 0 = pix-clk is high-active
34 * 1 = pic-clk is low-active
35 */
36#define HSYNC_INVERT (0x01 << 21) /*
37 * 0 = HSYNC is active high
38 * 1 = HSYNC is avtive low
39 */
40#define VSYNC_INVERT (0x01 << 20) /*
41 * 0 = VSYNC is active high
42 * 1 = VSYNC is active low
43 */
44
45struct am335x_lcdpanel {
46 unsigned int hactive; /* Horizontal active area */
47 unsigned int vactive; /* Vertical active area */
48 unsigned int bpp; /* bits per pixel */
49 unsigned int hfp; /* Horizontal front porch */
50 unsigned int hbp; /* Horizontal back porch */
51 unsigned int hsw; /* Horizontal Sync Pulse Width */
52 unsigned int vfp; /* Vertical front porch */
53 unsigned int vbp; /* Vertical back porch */
54 unsigned int vsw; /* Vertical Sync Pulse Width */
Hannes Schmelzer8a094f52018-01-09 19:01:34 +010055 unsigned int pxl_clk; /* Pixel clock */
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +010056 unsigned int pol; /* polarity of sync, clock signals */
Hannes Petermaier3b4e16e2015-02-03 13:22:23 +010057 unsigned int pup_delay; /*
58 * time in ms after power on to
59 * initialization of lcd-controller
60 * (VCC ramp up time)
61 */
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +010062 unsigned int pon_delay; /*
Hannes Petermaier3b4e16e2015-02-03 13:22:23 +010063 * time in ms after initialization of
64 * lcd-controller (pic stabilization)
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +010065 */
66 void (*panel_power_ctrl)(int); /* fp for power on/off display */
67};
68
69int am335xfb_init(struct am335x_lcdpanel *panel);
70
71#endif /* AM335X_FB_H */