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gerrit.cesnet.cz / github / trini / u-boot / 1f2a9970109cebf7446e0503b10b71f8673045ee / . / drivers / net / sk98lin / skgeinit.c
blob: a18dc0a48862a370cfbf5894227e64bf81940956 [file] [log] [blame]
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1/******************************************************************************
2 *
3 * Name: skgeinit.c
4 * Project: GEnesis, PCI Gigabit Ethernet Adapter
5 * Version: $Revision: 1.85 $
6 * Date: $Date: 2003/02/05 15:30:33 $
7 * Purpose: Contains functions to initialize the GE HW
8 *
9 ******************************************************************************/
10
11/******************************************************************************
12 *
13 * (C)Copyright 1998-2003 SysKonnect GmbH.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * The information in this file is provided "AS IS" without warranty.
21 *
22 ******************************************************************************/
23
24/******************************************************************************
25 *
26 * History:
27 *
28 * $Log: skgeinit.c,v $
29 * Revision 1.85 2003/02/05 15:30:33 rschmidt
30 * Corrected setting of GIHstClkFact (Host Clock Factor) and
31 * GIPollTimerVal (Descr. Poll Timer Init Value) for YUKON.
32 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]33 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]34 * Revision 1.84 2003/01/28 09:57:25 rschmidt
35 * Added detection of YUKON-Lite Rev. A0 (stored in GIYukonLite).
36 * Disabled Rx GMAC FIFO Flush for YUKON-Lite Rev. A0.
37 * Added support for CLK_RUN (YUKON-Lite).
38 * Added additional check of PME from D3cold for setting GIVauxAvail.
39 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]40 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]41 * Revision 1.83 2002/12/17 16:15:41 rschmidt
42 * Added default setting of PhyType (Copper) for YUKON.
43 * Added define around check for HW self test results.
44 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]45 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]46 * Revision 1.82 2002/12/05 13:40:21 rschmidt
47 * Added setting of Rx GMAC FIFO Flush Mask register.
48 * Corrected PhyType with new define SK_PHY_MARV_FIBER when
49 * YUKON Fiber board was found.
50 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]51 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]52 * Revision 1.81 2002/11/15 12:48:35 rschmidt
53 * Replaced message SKERR_HWI_E018 with SKERR_HWI_E024 for Rx queue error
54 * in SkGeStopPort().
55 * Added init for pAC->GIni.GIGenesis with SK_FALSE in YUKON-branch.
56 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]57 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]58 * Revision 1.80 2002/11/12 17:28:30 rschmidt
59 * Initialized GIPciSlot64 and GIPciClock66 in SkGeInit1().
60 * Reduced PCI FIFO watermarks for 32bit/33MHz bus in SkGeInitBmu().
61 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]62 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]63 * Revision 1.79 2002/10/21 09:31:02 mkarl
64 * Changed SkGeInitAssignRamToQueues(), removed call to
65 * SkGeInitAssignRamToQueues in SkGeInit1 and fixed compiler warning in
66 * SkGeInit1.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]67 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]68 * Revision 1.78 2002/10/16 15:55:07 mkarl
69 * Fixed a bug in SkGeInitAssignRamToQueues.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]70 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]71 * Revision 1.77 2002/10/14 15:07:22 rschmidt
72 * Corrected timeout handling for Rx queue in SkGeStopPort() (#10748)
73 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]74 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]75 * Revision 1.76 2002/10/11 09:24:38 mkarl
76 * Added check for HW self test results.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]77 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]78 * Revision 1.75 2002/10/09 16:56:44 mkarl
79 * Now call SkGeInitAssignRamToQueues() in Init Level 1 in order to assign
80 * the adapter memory to the queues. This default assignment is not suitable
81 * for dual net mode.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]82 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]83 * Revision 1.74 2002/09/12 08:45:06 rwahl
84 * Set defaults for PMSCap, PLinkSpeed & PLinkSpeedCap dependent on PHY.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]85 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]86 * Revision 1.73 2002/08/16 15:19:45 rschmidt
87 * Corrected check for Tx queues in SkGeCheckQSize().
88 * Added init for new entry GIGenesis and GICopperType
89 * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis.
90 * Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]91 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]92 * Revision 1.72 2002/08/12 13:38:55 rschmidt
93 * Added check if VAUX is available (stored in GIVauxAvail)
94 * Initialized PLinkSpeedCap in Port struct with SK_LSPEED_CAP_1000MBPS
95 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]96 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]97 * Revision 1.71 2002/08/08 16:32:58 rschmidt
98 * Added check for Tx queues in SkGeCheckQSize().
99 * Added start of Time Stamp Timer (YUKON) in SkGeInit2().
100 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]101 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]102 * Revision 1.70 2002/07/23 16:04:26 rschmidt
103 * Added init for GIWolOffs (HW-Bug in YUKON 1st rev.)
104 * Minor changes
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]105 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]106 * Revision 1.69 2002/07/17 17:07:08 rwahl
107 * - SkGeInit1(): fixed PHY type debug output; corrected init of GIFunc
108 * table & GIMacType.
109 * - Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]110 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]111 * Revision 1.68 2002/07/15 18:38:31 rwahl
112 * Added initialization for MAC type dependent function table.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]113 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]114 * Revision 1.67 2002/07/15 15:45:39 rschmidt
115 * Added Tx Store & Forward for YUKON (GMAC Tx FIFO is only 1 kB)
116 * Replaced SK_PHY_MARV by SK_PHY_MARV_COPPER
117 * Editorial changes
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]118 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]119 * Revision 1.66 2002/06/10 09:35:08 rschmidt
120 * Replaced C++ comments (//)
121 * Editorial changes
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]122 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]123 * Revision 1.65 2002/06/05 08:33:37 rschmidt
124 * Changed GIRamSize and Reset sequence for YUKON.
125 * SkMacInit() replaced by SkXmInitMac() resp. SkGmInitMac()
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]126 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]127 * Revision 1.64 2002/04/25 13:03:20 rschmidt
128 * Changes for handling YUKON.
129 * Removed reference to xmac_ii.h (not necessary).
130 * Moved all defines into header file.
131 * Replaced all SkXm...() functions with SkMac...() to handle also
132 * YUKON's GMAC.
133 * Added handling for GMAC FIFO in SkGeInitMacFifo(), SkGeStopPort().
134 * Removed 'goto'-directive from SkGeCfgSync(), SkGeCheckQSize().
135 * Replaced all XMAC-access macros by functions: SkMacRxTxDisable(),
136 * SkMacFlushTxFifo().
137 * Optimized timeout handling in SkGeStopPort().
138 * Initialized PLinkSpeed in Port struct with SK_LSPEED_AUTO.
139 * Release of GMAC Link Control reset in SkGeInit1().
140 * Initialized GIChipId and GIChipRev in GE Init structure.
141 * Added GIRamSize and PhyType values for YUKON.
142 * Removed use of PRxCmd to setup XMAC.
143 * Moved setting of XM_RX_DIS_CEXT to SkXmInitMac().
144 * Use of SkGeXmitLED() only for GENESIS.
145 * Changes for V-CPU support.
146 * Editorial changes.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]147 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]148 * Revision 1.63 2001/04/05 11:02:09 rassmann
149 * Stop Port check of the STOP bit did not take 2/18 sec as wanted.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]150 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]151 * Revision 1.62 2001/02/07 07:54:21 rassmann
152 * Corrected copyright.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]153 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]154 * Revision 1.61 2001/01/31 15:31:40 gklug
155 * fix: problem with autosensing an SR8800 switch
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]156 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]157 * Revision 1.60 2000/10/18 12:22:21 cgoos
158 * Added workaround for half duplex hangup.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]159 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]160 * Revision 1.59 2000/10/10 11:22:06 gklug
161 * add: in manual half duplex mode ignore carrier extension errors
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]162 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]163 * Revision 1.58 2000/10/02 14:10:27 rassmann
164 * Reading BCOM PHY after releasing reset until it returns a valid value.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]165 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]166 * Revision 1.57 2000/08/03 14:55:28 rassmann
167 * Waiting for I2C to be ready before de-initializing adapter
168 * (prevents sensors from hanging up).
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]169 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]170 * Revision 1.56 2000/07/27 12:16:48 gklug
171 * fix: Stop Port check of the STOP bit does now take 2/18 sec as wanted
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]172 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]173 * Revision 1.55 1999/11/22 13:32:26 cgoos
174 * Changed license header to GPL.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]175 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]176 * Revision 1.54 1999/10/26 07:32:54 malthoff
177 * Initialize PHWLinkUp with SK_FALSE. Required for Diagnostics.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]178 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]179 * Revision 1.53 1999/08/12 19:13:50 malthoff
180 * Fix for 1000BT. Do not owerwrite XM_MMU_CMD when
181 * disabling receiver and transmitter. Other bits
182 * may be lost.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]183 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]184 * Revision 1.52 1999/07/01 09:29:54 gklug
185 * fix: DoInitRamQueue needs pAC
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]186 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]187 * Revision 1.51 1999/07/01 08:42:21 gklug
188 * chg: use Store & forward for RAM buffer when Jumbos are used
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]189 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]190 * Revision 1.50 1999/05/27 13:19:38 cgoos
191 * Added Tx PCI watermark initialization.
192 * Removed Tx RAM queue Store & Forward setting.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]193 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]194 * Revision 1.49 1999/05/20 14:32:45 malthoff
195 * SkGeLinkLED() is completly removed now.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]196 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]197 * Revision 1.48 1999/05/19 07:28:24 cgoos
198 * SkGeLinkLED no more available for drivers.
199 * Changes for 1000Base-T.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]200 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]201 * Revision 1.47 1999/04/08 13:57:45 gklug
202 * add: Init of new port struct fiels PLinkResCt
203 * chg: StopPort Timer check
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]204 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]205 * Revision 1.46 1999/03/25 07:42:15 malthoff
206 * SkGeStopPort(): Add workaround for cache incoherency.
207 * Create error log entry, disable port, and
208 * exit loop if it does not terminate.
209 * Add XM_RX_LENERR_OK to the default value for the
210 * XMAC receive command register.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]211 *
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]212 * Revision 1.45 1999/03/12 16:24:47 malthoff
213 * Remove PPollRxD and PPollTxD.
214 * Add check for GIPollTimerVal.
215 *
216 * Revision 1.44 1999/03/12 13:40:23 malthoff
217 * Fix: SkGeXmitLED(), SK_LED_TST mode does not work.
218 * Add: Jumbo frame support.
219 * Chg: Resolution of parameter IntTime in SkGeCfgSync().
220 *
221 * Revision 1.43 1999/02/09 10:29:46 malthoff
222 * Bugfix: The previous modification again also for the second location.
223 *
224 * Revision 1.42 1999/02/09 09:35:16 malthoff
225 * Bugfix: The bits '66 MHz Capable' and 'NEWCAP are reset while
226 * clearing the error bits in the PCI status register.
227 *
228 * Revision 1.41 1999/01/18 13:07:02 malthoff
229 * Bugfix: Do not use CFG cycles after during Init- or Runtime, because
230 * they may not be available after Boottime.
231 *
232 * Revision 1.40 1999/01/11 12:40:49 malthoff
233 * Bug fix: PCI_STATUS: clearing error bits sets the UDF bit.
234 *
235 * Revision 1.39 1998/12/11 15:17:33 gklug
236 * chg: Init LipaAutoNeg with Unknown
237 *
238 * Revision 1.38 1998/12/10 11:02:57 malthoff
239 * Disable Error Log Message when calling SkGeInit(level 2)
240 * more than once.
241 *
242 * Revision 1.37 1998/12/07 12:18:25 gklug
243 * add: refinement of autosense mode: take into account the autoneg cap of LiPa
244 *
245 * Revision 1.36 1998/12/07 07:10:39 gklug
246 * fix: init values of LinkBroken/ Capabilities for management
247 *
248 * Revision 1.35 1998/12/02 10:56:20 gklug
249 * fix: do NOT init LoinkSync Counter.
250 *
251 * Revision 1.34 1998/12/01 10:53:21 gklug
252 * add: init of additional Counters for workaround
253 *
254 * Revision 1.33 1998/12/01 10:00:49 gklug
255 * add: init PIsave var in Port struct
256 *
257 * Revision 1.32 1998/11/26 14:50:40 gklug
258 * chg: Default is autosensing with AUTOFULL mode
259 *
260 * Revision 1.31 1998/11/25 15:36:16 gklug
261 * fix: do NOT stop LED Timer when port should be stopped
262 *
263 * Revision 1.30 1998/11/24 13:15:28 gklug
264 * add: Init PCkeckPar struct member
265 *
266 * Revision 1.29 1998/11/18 13:19:27 malthoff
267 * Disable packet arbiter timeouts on receive side.
268 * Use maximum timeout value for packet arbiter
269 * transmit timeouts.
270 * Add TestStopBit() function to handle stop RX/TX
271 * problem with active descriptor poll timers.
272 * Bug Fix: Descriptor Poll Timer not started, because
273 * GIPollTimerVal was initialized with 0.
274 *
275 * Revision 1.28 1998/11/13 14:24:26 malthoff
276 * Bug Fix: SkGeStopPort() may hang if a Packet Arbiter Timout
277 * is pending or occurs while waiting for TX_STOP and RX_STOP.
278 * The PA timeout is cleared now while waiting for TX- or RX_STOP.
279 *
280 * Revision 1.27 1998/11/02 11:04:36 malthoff
281 * fix the last fix
282 *
283 * Revision 1.26 1998/11/02 10:37:03 malthoff
284 * Fix: SkGePollTxD() enables always the synchronounous poll timer.
285 *
286 * Revision 1.25 1998/10/28 07:12:43 cgoos
287 * Fixed "LED_STOP" in SkGeLnkSyncCnt, "== SK_INIT_IO" in SkGeInit.
288 * Removed: Reset of RAM Interface in SkGeStopPort.
289 *
290 * Revision 1.24 1998/10/27 08:13:12 malthoff
291 * Remove temporary code.
292 *
293 * Revision 1.23 1998/10/26 07:45:03 malthoff
294 * Add Address Calculation Workaround: If the EPROM byte
295 * Id is 3, the address offset is 512 kB.
296 * Initialize default values for PLinkMode and PFlowCtrlMode.
297 *
298 * Revision 1.22 1998/10/22 09:46:47 gklug
299 * fix SysKonnectFileId typo
300 *
301 * Revision 1.21 1998/10/20 12:11:56 malthoff
302 * Don't dendy the Queue config if the size of the unused
303 * Rx qeueu is zero.
304 *
305 * Revision 1.20 1998/10/19 07:27:58 malthoff
306 * SkGeInitRamIface() is public to be called by diagnostics.
307 *
308 * Revision 1.19 1998/10/16 13:33:45 malthoff
309 * Fix: enabling descriptor polling is not allowed until
310 * the descriptor addresses are set. Descriptor polling
311 * must be handled by the driver.
312 *
313 * Revision 1.18 1998/10/16 10:58:27 malthoff
314 * Remove temp. code for Diag prototype.
315 * Remove lint warning for dummy reads.
316 * Call SkGeLoadLnkSyncCnt() during SkGeInitPort().
317 *
318 * Revision 1.17 1998/10/14 09:16:06 malthoff
319 * Change parameter LimCount and programming of
320 * the limit counter in SkGeCfgSync().
321 *
322 * Revision 1.16 1998/10/13 09:21:16 malthoff
323 * Don't set XM_RX_SELF_RX in RxCmd Reg, because it's
324 * like a Loopback Mode in half duplex.
325 *
326 * Revision 1.15 1998/10/09 06:47:40 malthoff
327 * SkGeInitMacArb(): set recovery counters init value
328 * to zero although this counters are not uesd.
329 * Bug fix in Rx Upper/Lower Pause Threshold calculation.
330 * Add XM_RX_SELF_RX to RxCmd.
331 *
332 * Revision 1.14 1998/10/06 15:15:53 malthoff
333 * Make sure no pending IRQ is cleared in SkGeLoadLnkSyncCnt().
334 *
335 * Revision 1.13 1998/10/06 14:09:36 malthoff
336 * Add SkGeLoadLnkSyncCnt(). Modify
337 * the 'port stopped' condition according
338 * to the current problem report.
339 *
340 * Revision 1.12 1998/10/05 08:17:21 malthoff
341 * Add functions: SkGePollRxD(), SkGePollTxD(),
342 * DoCalcAddr(), SkGeCheckQSize(),
343 * DoInitRamQueue(), and SkGeCfgSync().
344 * Add coding for SkGeInitMacArb(), SkGeInitPktArb(),
345 * SkGeInitMacFifo(), SkGeInitRamBufs(),
346 * SkGeInitRamIface(), and SkGeInitBmu().
347 *
348 * Revision 1.11 1998/09/29 08:26:29 malthoff
349 * bug fix: SkGeInit0() 'i' should be increment.
350 *
351 * Revision 1.10 1998/09/28 13:19:01 malthoff
352 * Coding time: Save the done work.
353 * Modify SkGeLinkLED(), add SkGeXmitLED(),
354 * define SkGeCheckQSize(), SkGeInitMacArb(),
355 * SkGeInitPktArb(), SkGeInitMacFifo(),
356 * SkGeInitRamBufs(), SkGeInitRamIface(),
357 * and SkGeInitBmu(). Do coding for SkGeStopPort(),
358 * SkGeInit1(), SkGeInit2(), and SkGeInit3().
359 * Do coding for SkGeDinit() and SkGeInitPort().
360 *
361 * Revision 1.9 1998/09/16 14:29:05 malthoff
362 * Some minor changes.
363 *
364 * Revision 1.8 1998/09/11 05:29:14 gklug
365 * add: init state of a port
366 *
367 * Revision 1.7 1998/09/04 09:26:25 malthoff
368 * Short temporary modification.
369 *
370 * Revision 1.6 1998/09/04 08:27:59 malthoff
371 * Remark the do-while in StopPort() because it never ends
372 * without a GE adapter.
373 *
374 * Revision 1.5 1998/09/03 14:05:45 malthoff
375 * Change comment for SkGeInitPort(). Do not
376 * repair the queue sizes if invalid.
377 *
378 * Revision 1.4 1998/09/03 10:03:19 malthoff
379 * Implement the new interface according to the
380 * reviewed interface specification.
381 *
382 * Revision 1.3 1998/08/19 09:11:25 gklug
383 * fix: struct are removed from c-source (see CCC)
384 *
385 * Revision 1.2 1998/07/28 12:33:58 malthoff
386 * Add 'IoC' parameter in function declaration and SK IO macros.
387 *
388 * Revision 1.1 1998/07/23 09:48:57 malthoff
389 * Creation. First dummy 'C' file.
390 * SkGeInit(Level 0) is card_start for GE.
391 * SkGeDeInit() is card_stop for GE.
392 *
393 *
394 ******************************************************************************/
395
wdenk149dded2003-09-10 18:20:28 +0000[diff] [blame]396#include <config.h>
397
398#ifdef CONFIG_SK98
399
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]400#include "h/skdrv1st.h"
401#include "h/skdrv2nd.h"
402
403/* global variables ***********************************************************/
404
405/* local variables ************************************************************/
406
407static const char SysKonnectFileId[] =
408 "@(#)$Id: skgeinit.c,v 1.85 2003/02/05 15:30:33 rschmidt Exp $ (C) SK ";
409
410struct s_QOffTab {
411 int RxQOff; /* Receive Queue Address Offset */
412 int XsQOff; /* Sync Tx Queue Address Offset */
413 int XaQOff; /* Async Tx Queue Address Offset */
414};
415static struct s_QOffTab QOffTab[] = {
416 {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2}
417};
418
419
420/******************************************************************************
421 *
422 * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring
423 *
424 * Description:
425 * Enable or disable the descriptor polling of the receive descriptor
426 * ring (RxD) for port 'Port'.
427 * The new configuration is *not* saved over any SkGeStopPort() and
428 * SkGeInitPort() calls.
429 *
430 * Returns:
431 * nothing
432 */
433void SkGePollRxD(
434SK_AC *pAC, /* adapter context */
435SK_IOC IoC, /* IO context */
436int Port, /* Port Index (MAC_1 + n) */
437SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
438{
439 SK_GEPORT *pPrt;
440
441 pPrt = &pAC->GIni.GP[Port];
442
443 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (PollRxD) ?
444 CSR_ENA_POL : CSR_DIS_POL);
445} /* SkGePollRxD */
446
447
448/******************************************************************************
449 *
450 * SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings
451 *
452 * Description:
453 * Enable or disable the descriptor polling of the transmit descriptor
454 * ring(s) (TxD) for port 'Port'.
455 * The new configuration is *not* saved over any SkGeStopPort() and
456 * SkGeInitPort() calls.
457 *
458 * Returns:
459 * nothing
460 */
461void SkGePollTxD(
462SK_AC *pAC, /* adapter context */
463SK_IOC IoC, /* IO context */
464int Port, /* Port Index (MAC_1 + n) */
465SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
466{
467 SK_GEPORT *pPrt;
468 SK_U32 DWord;
469
470 pPrt = &pAC->GIni.GP[Port];
471
472 DWord = (PollTxD) ? CSR_ENA_POL : CSR_DIS_POL;
473
474 if (pPrt->PXSQSize != 0) {
475 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord);
476 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]477
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]478 if (pPrt->PXAQSize != 0) {
479 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord);
480 }
481} /* SkGePollTxD */
482
483
484/******************************************************************************
485 *
486 * SkGeYellowLED() - Switch the yellow LED on or off.
487 *
488 * Description:
489 * Switch the yellow LED on or off.
490 *
491 * Note:
492 * This function may be called any time after SkGeInit(Level 1).
493 *
494 * Returns:
495 * nothing
496 */
497void SkGeYellowLED(
498SK_AC *pAC, /* adapter context */
499SK_IOC IoC, /* IO context */
500int State) /* yellow LED state, 0 = OFF, 0 != ON */
501{
502 if (State == 0) {
503 /* Switch yellow LED OFF */
504 SK_OUT8(IoC, B0_LED, LED_STAT_OFF);
505 }
506 else {
507 /* Switch yellow LED ON */
508 SK_OUT8(IoC, B0_LED, LED_STAT_ON);
509 }
510} /* SkGeYellowLED */
511
512
513/******************************************************************************
514 *
515 * SkGeXmitLED() - Modify the Operational Mode of a transmission LED.
516 *
517 * Description:
518 * The Rx or Tx LED which is specified by 'Led' will be
519 * enabled, disabled or switched on in test mode.
520 *
521 * Note:
522 * 'Led' must contain the address offset of the LEDs INI register.
523 *
524 * Usage:
525 * SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
526 *
527 * Returns:
528 * nothing
529 */
530void SkGeXmitLED(
531SK_AC *pAC, /* adapter context */
532SK_IOC IoC, /* IO context */
533int Led, /* offset to the LED Init Value register */
534int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
535{
536 SK_U32 LedIni;
537
538 switch (Mode) {
539 case SK_LED_ENA:
540 LedIni = SK_XMIT_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
541 SK_OUT32(IoC, Led + XMIT_LED_INI, LedIni);
542 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START);
543 break;
544 case SK_LED_TST:
545 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_ON);
546 SK_OUT32(IoC, Led + XMIT_LED_CNT, 100);
547 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START);
548 break;
549 case SK_LED_DIS:
550 default:
551 /*
552 * Do NOT stop the LED Timer here. The LED might be
553 * in on state. But it needs to go off.
554 */
555 SK_OUT32(IoC, Led + XMIT_LED_CNT, 0);
556 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF);
557 break;
558 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]559
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]560 /*
561 * 1000BT: The Transmit LED is driven by the PHY.
562 * But the default LED configuration is used for
563 * Level One and Broadcom PHYs.
564 * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
565 * (In this case it has to be added here. But we will see. XXX)
566 */
567} /* SkGeXmitLED */
568
569
570/******************************************************************************
571 *
572 * DoCalcAddr() - Calculates the start and the end address of a queue.
573 *
574 * Description:
575 * This function calculates the start and the end address of a queue.
576 * Afterwards the 'StartVal' is incremented to the next start position.
577 * If the port is already initialized the calculated values
578 * will be checked against the configured values and an
579 * error will be returned, if they are not equal.
580 * If the port is not initialized the values will be written to
581 * *StartAdr and *EndAddr.
582 *
583 * Returns:
584 * 0: success
585 * 1: configuration error
586 */
587static int DoCalcAddr(
588SK_AC *pAC, /* adapter context */
589SK_GEPORT *pPrt, /* port index */
590int QuSize, /* size of the queue to configure in kB */
591SK_U32 *StartVal, /* start value for address calculation */
592SK_U32 *QuStartAddr, /* start addr to calculate */
593SK_U32 *QuEndAddr) /* end address to calculate */
594{
595 SK_U32 EndVal;
596 SK_U32 NextStart;
597 int Rtv;
598
599 Rtv = 0;
600 if (QuSize == 0) {
601 EndVal = *StartVal;
602 NextStart = EndVal;
603 }
604 else {
605 EndVal = *StartVal + ((SK_U32)QuSize * 1024) - 1;
606 NextStart = EndVal + 1;
607 }
608
609 if (pPrt->PState >= SK_PRT_INIT) {
610 if (*StartVal != *QuStartAddr || EndVal != *QuEndAddr) {
611 Rtv = 1;
612 }
613 }
614 else {
615 *QuStartAddr = *StartVal;
616 *QuEndAddr = EndVal;
617 }
618
619 *StartVal = NextStart;
620 return(Rtv);
621} /* DoCalcAddr */
622
623/******************************************************************************
624 *
625 * SkGeInitAssignRamToQueues() - allocate default queue sizes
626 *
627 * Description:
628 * This function assigns the memory to the different queues and ports.
629 * When DualNet is set to SK_TRUE all ports get the same amount of memory.
630 * Otherwise the first port gets most of the memory and all the
631 * other ports just the required minimum.
632 * This function can only be called when pAC->GIni.GIRamSize and
633 * pAC->GIni.GIMacsFound have been initialized, usually this happens
634 * at init level 1
635 *
636 * Returns:
637 * 0 - ok
638 * 1 - invalid input values
639 * 2 - not enough memory
640 */
641
642int SkGeInitAssignRamToQueues(
643SK_AC *pAC, /* Adapter context */
644int ActivePort, /* Active Port in RLMT mode */
645SK_BOOL DualNet) /* adapter context */
646{
647 int i;
648 int UsedKilobytes; /* memory already assigned */
649 int ActivePortKilobytes; /* memory available for active port */
650 SK_GEPORT *pGePort;
651
652 UsedKilobytes = 0;
653
654 if (ActivePort >= pAC->GIni.GIMacsFound) {
655 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
656 ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n",
657 ActivePort));
658 return(1);
659 }
660 if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) +
661 ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) {
662 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
663 ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n",
664 pAC->GIni.GIRamSize));
665 return(2);
666 }
667
668
669 if (DualNet) {
670 /* every port gets the same amount of memory */
671 ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound;
672 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
673
674 pGePort = &pAC->GIni.GP[i];
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]675
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]676 /* take away the minimum memory for active queues */
677 ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
678
679 /* receive queue gets the minimum + 80% of the rest */
680 pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((
681 ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100))
682 + SK_MIN_RXQ_SIZE;
683
684 ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
685
686 /* synchronous transmit queue */
687 pGePort->PXSQSize = 0;
688
689 /* asynchronous transmit queue */
690 pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes +
691 SK_MIN_TXQ_SIZE);
692 }
693 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]694 else {
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]695 /* Rlmt Mode or single link adapter */
696
697 /* Set standby queue size defaults for all standby ports */
698 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
699
700 if (i != ActivePort) {
701 pGePort = &pAC->GIni.GP[i];
702
703 pGePort->PRxQSize = SK_MIN_RXQ_SIZE;
704 pGePort->PXAQSize = SK_MIN_TXQ_SIZE;
705 pGePort->PXSQSize = 0;
706
707 /* Count used RAM */
708 UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize;
709 }
710 }
711 /* what's left? */
712 ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes;
713
714 /* assign it to the active port */
715 /* first take away the minimum memory */
716 ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
717 pGePort = &pAC->GIni.GP[ActivePort];
718
719 /* receive queue get's the minimum + 80% of the rest */
720 pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes *
721 (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE;
722
723 ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
724
725 /* synchronous transmit queue */
726 pGePort->PXSQSize = 0;
727
728 /* asynchronous transmit queue */
729 pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) +
730 SK_MIN_TXQ_SIZE;
731 }
732#ifdef VCPU
733 VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n",
734 pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize);
735#endif /* VCPU */
736
737 return(0);
738} /* SkGeInitAssignRamToQueues */
739
740/******************************************************************************
741 *
742 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
743 *
744 * Description:
745 * This function verifies the Queue Size Configuration specified
746 * in the variables PRxQSize, PXSQSize, and PXAQSize of all
747 * used ports.
748 * This requirements must be fullfilled to have a valid configuration:
749 * - The size of all queues must not exceed GIRamSize.
750 * - The queue sizes must be specified in units of 8 kB.
751 * - The size of Rx queues of available ports must not be
752 * smaller than 16 kB.
753 * - The size of at least one Tx queue (synch. or asynch.)
754 * of available ports must not be smaller than 16 kB
755 * when Jumbo Frames are used.
756 * - The RAM start and end addresses must not be changed
757 * for ports which are already initialized.
758 * Furthermore SkGeCheckQSize() defines the Start and End Addresses
759 * of all ports and stores them into the HWAC port structure.
760 *
761 * Returns:
762 * 0: Queue Size Configuration valid
763 * 1: Queue Size Configuration invalid
764 */
765static int SkGeCheckQSize(
766SK_AC *pAC, /* adapter context */
767int Port) /* port index */
768{
769 SK_GEPORT *pPrt;
770 int UsedMem; /* total memory used (max. found ports) */
771 int i;
772 int Rtv;
773 int Rtv2;
774 SK_U32 StartAddr;
775
776 UsedMem = 0;
777 Rtv = 0;
778 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
779 pPrt = &pAC->GIni.GP[i];
780
781 if ((pPrt->PRxQSize & QZ_UNITS) != 0 ||
782 (pPrt->PXSQSize & QZ_UNITS) != 0 ||
783 (pPrt->PXAQSize & QZ_UNITS) != 0) {
784
785 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
786 return(1);
787 }
788
789 if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
790 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG);
791 return(1);
792 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]793
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]794 /*
795 * the size of at least one Tx queue (synch. or asynch.) has to be > 0.
796 * if Jumbo Frames are used, this size has to be >= 16 kB.
797 */
798 if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) ||
799 (pAC->GIni.GIPortUsage == SK_JUMBO_LINK &&
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]800 ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]801 (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) {
802 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG);
803 return(1);
804 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]805
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]806 UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
807 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]808
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]809 if (UsedMem > pAC->GIni.GIRamSize) {
810 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
811 return(1);
812 }
813
814 /* Now start address calculation */
815 StartAddr = pAC->GIni.GIRamOffs;
816 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
817 pPrt = &pAC->GIni.GP[i];
818
819 /* Calculate/Check values for the receive queue */
820 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr,
821 &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd);
822 Rtv |= Rtv2;
823
824 /* Calculate/Check values for the synchronous Tx queue */
825 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXSQSize, &StartAddr,
826 &pPrt->PXsQRamStart, &pPrt->PXsQRamEnd);
827 Rtv |= Rtv2;
828
829 /* Calculate/Check values for the asynchronous Tx queue */
830 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXAQSize, &StartAddr,
831 &pPrt->PXaQRamStart, &pPrt->PXaQRamEnd);
832 Rtv |= Rtv2;
833
834 if (Rtv) {
835 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E013, SKERR_HWI_E013MSG);
836 return(1);
837 }
838 }
839
840 return(0);
841} /* SkGeCheckQSize */
842
843
844/******************************************************************************
845 *
846 * SkGeInitMacArb() - Initialize the MAC Arbiter
847 *
848 * Description:
849 * This function initializes the MAC Arbiter.
850 * It must not be called if there is still an
851 * initialized or active port.
852 *
853 * Returns:
854 * nothing
855 */
856static void SkGeInitMacArb(
857SK_AC *pAC, /* adapter context */
858SK_IOC IoC) /* IO context */
859{
860 /* release local reset */
861 SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR);
862
863 /* configure timeout values */
864 SK_OUT8(IoC, B3_MA_TOINI_RX1, SK_MAC_TO_53);
865 SK_OUT8(IoC, B3_MA_TOINI_RX2, SK_MAC_TO_53);
866 SK_OUT8(IoC, B3_MA_TOINI_TX1, SK_MAC_TO_53);
867 SK_OUT8(IoC, B3_MA_TOINI_TX2, SK_MAC_TO_53);
868
869 SK_OUT8(IoC, B3_MA_RCINI_RX1, 0);
870 SK_OUT8(IoC, B3_MA_RCINI_RX2, 0);
871 SK_OUT8(IoC, B3_MA_RCINI_TX1, 0);
872 SK_OUT8(IoC, B3_MA_RCINI_TX2, 0);
873
874 /* recovery values are needed for XMAC II Rev. B2 only */
875 /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */
876
877 /*
878 * There is no start or enable button to push, therefore
879 * the MAC arbiter is configured and enabled now.
880 */
881} /* SkGeInitMacArb */
882
883
884/******************************************************************************
885 *
886 * SkGeInitPktArb() - Initialize the Packet Arbiter
887 *
888 * Description:
889 * This function initializes the Packet Arbiter.
890 * It must not be called if there is still an
891 * initialized or active port.
892 *
893 * Returns:
894 * nothing
895 */
896static void SkGeInitPktArb(
897SK_AC *pAC, /* adapter context */
898SK_IOC IoC) /* IO context */
899{
900 /* release local reset */
901 SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR);
902
903 /* configure timeout values */
904 SK_OUT16(IoC, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
905 SK_OUT16(IoC, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
906 SK_OUT16(IoC, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
907 SK_OUT16(IoC, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
908
909 /*
910 * enable timeout timers if jumbo frames not used
911 * NOTE: the packet arbiter timeout interrupt is needed for
912 * half duplex hangup workaround
913 */
914 if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) {
915 if (pAC->GIni.GIMacsFound == 1) {
916 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1);
917 }
918 else {
919 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1 | PA_ENA_TO_TX2);
920 }
921 }
922} /* SkGeInitPktArb */
923
924
925/******************************************************************************
926 *
927 * SkGeInitMacFifo() - Initialize the MAC FIFOs
928 *
929 * Description:
930 * Initialize all MAC FIFOs of the specified port
931 *
932 * Returns:
933 * nothing
934 */
935static void SkGeInitMacFifo(
936SK_AC *pAC, /* adapter context */
937SK_IOC IoC, /* IO context */
938int Port) /* Port Index (MAC_1 + n) */
939{
940 SK_U16 Word;
941#ifdef VCPU
942 SK_U32 DWord;
943#endif /* VCPU */
944 /*
945 * For each FIFO:
946 * - release local reset
947 * - use default value for MAC FIFO size
948 * - setup defaults for the control register
949 * - enable the FIFO
950 */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]951
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]952 Word = GMF_RX_CTRL_DEF;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]953
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]954 if (pAC->GIni.GIGenesis) {
955 /* Configure Rx MAC FIFO */
956 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR);
957 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF);
958 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]959
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]960 /* Configure Tx MAC FIFO */
961 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR);
962 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
963 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]964
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]965 /* Enable frame flushing if jumbo frames used */
966 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
967 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
968 }
969 }
970 else {
971 /* set Rx GMAC FIFO Flush Mask */
972 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]973
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]974 if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) {
975
976 Word &= ~GMF_RX_F_FL_ON;
977 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]978
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]979 /* Configure Rx MAC FIFO */
980 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
981 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]982
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]983 /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */
984 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]985
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]986 /* Configure Tx MAC FIFO */
987 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
988 SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]989
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]990#ifdef VCPU
991 SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord);
992 SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord);
993#endif /* VCPU */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]994
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]995 /* set Tx GMAC FIFO Almost Empty Threshold */
996/* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */
997 }
998} /* SkGeInitMacFifo */
999
1000
1001/******************************************************************************
1002 *
1003 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
1004 *
1005 * Description:
1006 * This function starts the Link Sync Counter of the specified
1007 * port and enables the generation of an Link Sync IRQ.
1008 * The Link Sync Counter may be used to detect an active link,
1009 * if autonegotiation is not used.
1010 *
1011 * Note:
1012 * o To ensure receiving the Link Sync Event the LinkSyncCounter
1013 * should be initialized BEFORE clearing the XMAC's reset!
1014 * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this
1015 * function.
1016 *
1017 * Returns:
1018 * nothing
1019 */
1020void SkGeLoadLnkSyncCnt(
1021SK_AC *pAC, /* adapter context */
1022SK_IOC IoC, /* IO context */
1023int Port, /* Port Index (MAC_1 + n) */
1024SK_U32 CntVal) /* Counter value */
1025{
1026 SK_U32 OrgIMsk;
1027 SK_U32 NewIMsk;
1028 SK_U32 ISrc;
1029 SK_BOOL IrqPend;
1030
1031 /* stop counter */
1032 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP);
1033
1034 /*
1035 * ASIC problem:
1036 * Each time starting the Link Sync Counter an IRQ is generated
1037 * by the adapter. See problem report entry from 21.07.98
1038 *
1039 * Workaround: Disable Link Sync IRQ and clear the unexpeced IRQ
1040 * if no IRQ is already pending.
1041 */
1042 IrqPend = SK_FALSE;
1043 SK_IN32(IoC, B0_ISRC, &ISrc);
1044 SK_IN32(IoC, B0_IMSK, &OrgIMsk);
1045 if (Port == MAC_1) {
1046 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1;
1047 if ((ISrc & IS_LNK_SYNC_M1) != 0) {
1048 IrqPend = SK_TRUE;
1049 }
1050 }
1051 else {
1052 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M2;
1053 if ((ISrc & IS_LNK_SYNC_M2) != 0) {
1054 IrqPend = SK_TRUE;
1055 }
1056 }
1057 if (!IrqPend) {
1058 SK_OUT32(IoC, B0_IMSK, NewIMsk);
1059 }
1060
1061 /* load counter */
1062 SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal);
1063
1064 /* start counter */
1065 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START);
1066
1067 if (!IrqPend) {
1068 /* clear the unexpected IRQ, and restore the interrupt mask */
1069 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ);
1070 SK_OUT32(IoC, B0_IMSK, OrgIMsk);
1071 }
1072} /* SkGeLoadLnkSyncCnt*/
1073
1074
1075/******************************************************************************
1076 *
1077 * SkGeCfgSync() - Configure synchronous bandwidth for this port.
1078 *
1079 * Description:
1080 * This function may be used to configure synchronous bandwidth
1081 * to the specified port. This may be done any time after
1082 * initializing the port. The configuration values are NOT saved
1083 * in the HWAC port structure and will be overwritten any
1084 * time when stopping and starting the port.
1085 * Any values for the synchronous configuration will be ignored
1086 * if the size of the synchronous queue is zero!
1087 *
1088 * The default configuration for the synchronous service is
1089 * TXA_ENA_FSYNC. This means if the size of
1090 * the synchronous queue is unequal zero but no specific
1091 * synchronous bandwidth is configured, the synchronous queue
1092 * will always have the 'unlimited' transmit priority!
1093 *
1094 * This mode will be restored if the synchronous bandwidth is
1095 * deallocated ('IntTime' = 0 and 'LimCount' = 0).
1096 *
1097 * Returns:
1098 * 0: success
1099 * 1: parameter configuration error
1100 * 2: try to configure quality of service although no
1101 * synchronous queue is configured
1102 */
1103int SkGeCfgSync(
1104SK_AC *pAC, /* adapter context */
1105SK_IOC IoC, /* IO context */
1106int Port, /* Port Index (MAC_1 + n) */
1107SK_U32 IntTime, /* Interval Timer Value in units of 8ns */
1108SK_U32 LimCount, /* Number of bytes to transfer during IntTime */
1109int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */
1110{
1111 int Rtv;
1112
1113 Rtv = 0;
1114
1115 /* check the parameters */
1116 if (LimCount > IntTime ||
1117 (LimCount == 0 && IntTime != 0) ||
1118 (LimCount != 0 && IntTime == 0)) {
1119
1120 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
1121 return(1);
1122 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1123
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1124 if (pAC->GIni.GP[Port].PXSQSize == 0) {
1125 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG);
1126 return(2);
1127 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1128
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1129 /* calculate register values */
1130 IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100;
1131 LimCount = LimCount / 8;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1132
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1133 if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) {
1134 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
1135 return(1);
1136 }
1137
1138 /*
1139 * - Enable 'Force Sync' to ensure the synchronous queue
1140 * has the priority while configuring the new values.
1141 * - Also 'disable alloc' to ensure the settings complies
1142 * to the SyncMode parameter.
1143 * - Disable 'Rate Control' to configure the new values.
1144 * - write IntTime and LimCount
1145 * - start 'Rate Control' and disable 'Force Sync'
1146 * if Interval Timer or Limit Counter not zero.
1147 */
1148 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
1149 TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1150
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1151 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime);
1152 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1153
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1154 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
1155 (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC)));
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1156
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1157 if (IntTime != 0 || LimCount != 0) {
1158 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC);
1159 }
1160
1161 return(0);
1162} /* SkGeCfgSync */
1163
1164
1165/******************************************************************************
1166 *
1167 * DoInitRamQueue() - Initialize the RAM Buffer Address of a single Queue
1168 *
1169 * Desccription:
1170 * If the queue is used, enable and initialize it.
1171 * Make sure the queue is still reset, if it is not used.
1172 *
1173 * Returns:
1174 * nothing
1175 */
1176static void DoInitRamQueue(
1177SK_AC *pAC, /* adapter context */
1178SK_IOC IoC, /* IO context */
1179int QuIoOffs, /* Queue IO Address Offset */
1180SK_U32 QuStartAddr, /* Queue Start Address */
1181SK_U32 QuEndAddr, /* Queue End Address */
1182int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
1183{
1184 SK_U32 RxUpThresVal;
1185 SK_U32 RxLoThresVal;
1186
1187 if (QuStartAddr != QuEndAddr) {
1188 /* calculate thresholds, assume we have a big Rx queue */
1189 RxUpThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_ULPP) / 8;
1190 RxLoThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_LLPP_B)/8;
1191
1192 /* build HW address format */
1193 QuStartAddr = QuStartAddr / 8;
1194 QuEndAddr = QuEndAddr / 8;
1195
1196 /* release local reset */
1197 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_CLR);
1198
1199 /* configure addresses */
1200 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_START), QuStartAddr);
1201 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_END), QuEndAddr);
1202 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_WP), QuStartAddr);
1203 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RP), QuStartAddr);
1204
1205 switch (QuType) {
1206 case SK_RX_SRAM_Q:
1207 /* configure threshold for small Rx Queue */
1208 RxLoThresVal += (SK_RB_LLPP_B - SK_RB_LLPP_S) / 8;
1209
1210 /* continue with SK_RX_BRAM_Q */
1211 case SK_RX_BRAM_Q:
1212 /* write threshold for Rx Queue */
1213
1214 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal);
1215 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal);
1216
1217 /* the high priority threshold not used */
1218 break;
1219 case SK_TX_RAM_Q:
1220 /*
1221 * Do NOT use Store & Forward under normal operation due to
1222 * performance optimization (GENESIS only).
1223 * But if Jumbo Frames are configured (XMAC Tx FIFO is only 4 kB)
1224 * or YUKON is used ((GMAC Tx FIFO is only 1 kB)
1225 * we NEED Store & Forward of the RAM buffer.
1226 */
1227 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK ||
1228 !pAC->GIni.GIGenesis) {
1229 /* enable Store & Forward Mode for the Tx Side */
1230 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD);
1231 }
1232 break;
1233 }
1234
1235 /* set queue operational */
1236 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_OP_MD);
1237 }
1238 else {
1239 /* ensure the queue is still disabled */
1240 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_SET);
1241 }
1242} /* DoInitRamQueue */
1243
1244
1245/******************************************************************************
1246 *
1247 * SkGeInitRamBufs() - Initialize the RAM Buffer Queues
1248 *
1249 * Description:
1250 * Initialize all RAM Buffer Queues of the specified port
1251 *
1252 * Returns:
1253 * nothing
1254 */
1255static void SkGeInitRamBufs(
1256SK_AC *pAC, /* adapter context */
1257SK_IOC IoC, /* IO context */
1258int Port) /* Port Index (MAC_1 + n) */
1259{
1260 SK_GEPORT *pPrt;
1261 int RxQType;
1262
1263 pPrt = &pAC->GIni.GP[Port];
1264
1265 if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
1266 RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
1267 }
1268 else {
1269 RxQType = SK_RX_BRAM_Q; /* big Rx Queue */
1270 }
1271
1272 DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
1273 pPrt->PRxQRamEnd, RxQType);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1274
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1275 DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
1276 pPrt->PXsQRamEnd, SK_TX_RAM_Q);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1277
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1278 DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
1279 pPrt->PXaQRamEnd, SK_TX_RAM_Q);
1280
1281} /* SkGeInitRamBufs */
1282
1283
1284/******************************************************************************
1285 *
1286 * SkGeInitRamIface() - Initialize the RAM Interface
1287 *
1288 * Description:
1289 * This function initializes the Adapters RAM Interface.
1290 *
1291 * Note:
1292 * This function is used in the diagnostics.
1293 *
1294 * Returns:
1295 * nothing
1296 */
1297void SkGeInitRamIface(
1298SK_AC *pAC, /* adapter context */
1299SK_IOC IoC) /* IO context */
1300{
1301 /* release local reset */
1302 SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR);
1303
1304 /* configure timeout values */
1305 SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53);
1306 SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53);
1307 SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53);
1308 SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53);
1309 SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53);
1310 SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53);
1311 SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53);
1312 SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53);
1313 SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53);
1314 SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53);
1315 SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53);
1316 SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53);
1317
1318} /* SkGeInitRamIface */
1319
1320
1321/******************************************************************************
1322 *
1323 * SkGeInitBmu() - Initialize the BMU state machines
1324 *
1325 * Description:
1326 * Initialize all BMU state machines of the specified port
1327 *
1328 * Returns:
1329 * nothing
1330 */
1331static void SkGeInitBmu(
1332SK_AC *pAC, /* adapter context */
1333SK_IOC IoC, /* IO context */
1334int Port) /* Port Index (MAC_1 + n) */
1335{
1336 SK_GEPORT *pPrt;
1337 SK_U32 RxWm;
1338 SK_U32 TxWm;
1339
1340 pPrt = &pAC->GIni.GP[Port];
1341
1342 RxWm = SK_BMU_RX_WM;
1343 TxWm = SK_BMU_TX_WM;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1344
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1345 if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
1346 /* for better performance */
1347 RxWm /= 2;
1348 TxWm /= 2;
1349 }
1350
1351 /* Rx Queue: Release all local resets and set the watermark */
1352 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
1353 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
1354
1355 /*
1356 * Tx Queue: Release all local resets if the queue is used !
1357 * set watermark
1358 */
1359 if (pPrt->PXSQSize != 0) {
1360 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
1361 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
1362 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1363
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1364 if (pPrt->PXAQSize != 0) {
1365 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
1366 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
1367 }
1368 /*
1369 * Do NOT enable the descriptor poll timers here, because
1370 * the descriptor addresses are not specified yet.
1371 */
1372} /* SkGeInitBmu */
1373
1374
1375/******************************************************************************
1376 *
1377 * TestStopBit() - Test the stop bit of the queue
1378 *
1379 * Description:
1380 * Stopping a queue is not as simple as it seems to be.
1381 * If descriptor polling is enabled, it may happen
1382 * that RX/TX stop is done and SV idle is NOT set.
1383 * In this case we have to issue another stop command.
1384 *
1385 * Returns:
1386 * The queues control status register
1387 */
1388static SK_U32 TestStopBit(
1389SK_AC *pAC, /* Adapter Context */
1390SK_IOC IoC, /* IO Context */
1391int QuIoOffs) /* Queue IO Address Offset */
1392{
1393 SK_U32 QuCsr; /* CSR contents */
1394
1395 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1396
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1397 if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
1398 /* Stop Descriptor overridden by start command */
1399 SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
1400
1401 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
1402 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1403
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1404 return(QuCsr);
1405} /* TestStopBit */
1406
1407
1408/******************************************************************************
1409 *
1410 * SkGeStopPort() - Stop the Rx/Tx activity of the port 'Port'.
1411 *
1412 * Description:
1413 * After calling this function the descriptor rings and Rx and Tx
1414 * queues of this port may be reconfigured.
1415 *
1416 * It is possible to stop the receive and transmit path separate or
1417 * both together.
1418 *
1419 * Dir = SK_STOP_TX Stops the transmit path only and resets the MAC.
1420 * The receive queue is still active and
1421 * the pending Rx frames may be still transferred
1422 * into the RxD.
1423 * SK_STOP_RX Stop the receive path. The tansmit path
1424 * has to be stopped once before.
1425 * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX
1426 *
1427 * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive.
1428 * SK_HARD_RST Resets the MAC and the PHY.
1429 *
1430 * Example:
1431 * 1) A Link Down event was signaled for a port. Therefore the activity
1432 * of this port should be stopped and a hardware reset should be issued
1433 * to enable the workaround of XMAC errata #2. But the received frames
1434 * should not be discarded.
1435 * ...
1436 * SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST);
1437 * (transfer all pending Rx frames)
1438 * SkGeStopPort(pAC, IoC, Port, SK_STOP_RX, SK_HARD_RST);
1439 * ...
1440 *
1441 * 2) An event was issued which request the driver to switch
1442 * the 'virtual active' link to an other already active port
1443 * as soon as possible. The frames in the receive queue of this
1444 * port may be lost. But the PHY must not be reset during this
1445 * event.
1446 * ...
1447 * SkGeStopPort(pAC, IoC, Port, SK_STOP_ALL, SK_SOFT_RST);
1448 * ...
1449 *
1450 * Extended Description:
1451 * If SK_STOP_TX is set,
1452 * o disable the MAC's receive and transmitter to prevent
1453 * from sending incomplete frames
1454 * o stop the port's transmit queues before terminating the
1455 * BMUs to prevent from performing incomplete PCI cycles
1456 * on the PCI bus
1457 * - The network Rx and Tx activity and PCI Tx transfer is
1458 * disabled now.
1459 * o reset the MAC depending on the RstMode
1460 * o Stop Interval Timer and Limit Counter of Tx Arbiter,
1461 * also disable Force Sync bit and Enable Alloc bit.
1462 * o perform a local reset of the port's Tx path
1463 * - reset the PCI FIFO of the async Tx queue
1464 * - reset the PCI FIFO of the sync Tx queue
1465 * - reset the RAM Buffer async Tx queue
1466 * - reset the RAM Buffer sync Tx queue
1467 * - reset the MAC Tx FIFO
1468 * o switch Link and Tx LED off, stop the LED counters
1469 *
1470 * If SK_STOP_RX is set,
1471 * o stop the port's receive queue
1472 * - The path data transfer activity is fully stopped now.
1473 * o perform a local reset of the port's Rx path
1474 * - reset the PCI FIFO of the Rx queue
1475 * - reset the RAM Buffer receive queue
1476 * - reset the MAC Rx FIFO
1477 * o switch Rx LED off, stop the LED counter
1478 *
1479 * If all ports are stopped,
1480 * o reset the RAM Interface.
1481 *
1482 * Notes:
1483 * o This function may be called during the driver states RESET_PORT and
1484 * SWITCH_PORT.
1485 */
1486void SkGeStopPort(
1487SK_AC *pAC, /* adapter context */
1488SK_IOC IoC, /* I/O context */
1489int Port, /* port to stop (MAC_1 + n) */
1490int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
1491int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
1492{
1493#ifndef SK_DIAG
1494 SK_EVPARA Para;
1495#endif /* !SK_DIAG */
1496 SK_GEPORT *pPrt;
1497 SK_U32 DWord;
1498 SK_U32 XsCsr;
1499 SK_U32 XaCsr;
1500 SK_U64 ToutStart;
1501 int i;
1502 int ToutCnt;
1503
1504 pPrt = &pAC->GIni.GP[Port];
1505
1506 if ((Dir & SK_STOP_TX) != 0) {
1507 /* disable receiver and transmitter */
1508 SkMacRxTxDisable(pAC, IoC, Port);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1509
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1510 /* stop both transmit queues */
1511 /*
1512 * If the BMU is in the reset state CSR_STOP will terminate
1513 * immediately.
1514 */
1515 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP);
1516 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP);
1517
1518 ToutStart = SkOsGetTime(pAC);
1519 ToutCnt = 0;
1520 do {
1521 /*
1522 * Clear packet arbiter timeout to make sure
1523 * this loop will terminate.
1524 */
1525 SK_OUT16(IoC, B3_PA_CTRL, (Port == MAC_1) ? PA_CLR_TO_TX1 :
1526 PA_CLR_TO_TX2);
1527
1528 /*
1529 * If the transfer stucks at the MAC the STOP command will not
1530 * terminate if we don't flush the XMAC's transmit FIFO !
1531 */
1532 SkMacFlushTxFifo(pAC, IoC, Port);
1533
1534 XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
1535 XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
1536
1537 if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) {
1538 /*
1539 * Timeout of 1/18 second reached.
1540 * This needs to be checked at 1/18 sec only.
1541 */
1542 ToutCnt++;
1543 if (ToutCnt > 1) {
1544 /* Might be a problem when the driver event handler
1545 * calls StopPort again. XXX.
1546 */
1547
1548 /* Fatal Error, Loop aborted */
1549 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018,
1550 SKERR_HWI_E018MSG);
1551#ifndef SK_DIAG
1552 Para.Para64 = Port;
1553 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
1554#endif /* !SK_DIAG */
1555 return;
1556 }
1557 /*
1558 * Cache incoherency workaround: Assume a start command
1559 * has been lost while sending the frame.
1560 */
1561 ToutStart = SkOsGetTime(pAC);
1562
1563 if ((XsCsr & CSR_STOP) != 0) {
1564 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START);
1565 }
1566 if ((XaCsr & CSR_STOP) != 0) {
1567 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START);
1568 }
1569 }
1570
1571 /*
1572 * Because of the ASIC problem report entry from 21.08.1998 it is
1573 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
1574 */
1575 } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE ||
1576 (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
1577
1578 /* Reset the MAC depending on the RstMode */
1579 if (RstMode == SK_SOFT_RST) {
1580 SkMacSoftRst(pAC, IoC, Port);
1581 }
1582 else {
1583 SkMacHardRst(pAC, IoC, Port);
1584 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1585
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1586 /* Disable Force Sync bit and Enable Alloc bit */
1587 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
1588 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1589
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1590 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1591 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L);
1592 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L);
1593
1594 /* Perform a local reset of the port's Tx path */
1595
1596 /* Reset the PCI FIFO of the async Tx queue */
1597 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
1598 /* Reset the PCI FIFO of the sync Tx queue */
1599 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
1600 /* Reset the RAM Buffer async Tx queue */
1601 SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
1602 /* Reset the RAM Buffer sync Tx queue */
1603 SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1604
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1605 /* Reset Tx MAC FIFO */
1606 if (pAC->GIni.GIGenesis) {
1607 /* Note: MFF_RST_SET does NOT reset the XMAC ! */
1608 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_SET);
1609
1610 /* switch Link and Tx LED off, stop the LED counters */
1611 /* Link LED is switched off by the RLMT and the Diag itself */
1612 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS);
1613 }
1614 else {
1615 /* Reset TX MAC FIFO */
1616 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
1617 }
1618 }
1619
1620 if ((Dir & SK_STOP_RX) != 0) {
1621 /*
1622 * The RX Stop Command will not terminate if no buffers
1623 * are queued in the RxD ring. But it will always reach
1624 * the Idle state. Therefore we can use this feature to
1625 * stop the transfer of received packets.
1626 */
1627 /* stop the port's receive queue */
1628 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1629
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1630 i = 100;
1631 do {
1632 /*
1633 * Clear packet arbiter timeout to make sure
1634 * this loop will terminate
1635 */
1636 SK_OUT16(IoC, B3_PA_CTRL, (Port == MAC_1) ? PA_CLR_TO_RX1 :
1637 PA_CLR_TO_RX2);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1638
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1639 DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff);
1640
1641 /* timeout if i==0 (bug fix for #10748) */
1642 if (--i == 0) {
1643 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
1644 SKERR_HWI_E024MSG);
1645 break;
1646 }
1647 /*
1648 * because of the ASIC problem report entry from 21.08.98
1649 * it is required to wait until CSR_STOP is reset and
1650 * CSR_SV_IDLE is set.
1651 */
1652 } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
1653
1654 /* The path data transfer activity is fully stopped now */
1655
1656 /* Perform a local reset of the port's Rx path */
1657
1658 /* Reset the PCI FIFO of the Rx queue */
1659 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
1660 /* Reset the RAM Buffer receive queue */
1661 SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET);
1662
1663 /* Reset Rx MAC FIFO */
1664 if (pAC->GIni.GIGenesis) {
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1665
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1666 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET);
1667
1668 /* switch Rx LED off, stop the LED counter */
1669 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS);
1670 }
1671 else {
1672 /* Reset Rx MAC FIFO */
1673 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
1674 }
1675 }
1676} /* SkGeStopPort */
1677
1678
1679/******************************************************************************
1680 *
1681 * SkGeInit0() - Level 0 Initialization
1682 *
1683 * Description:
1684 * - Initialize the BMU address offsets
1685 *
1686 * Returns:
1687 * nothing
1688 */
1689static void SkGeInit0(
1690SK_AC *pAC, /* adapter context */
1691SK_IOC IoC) /* IO context */
1692{
1693 int i;
1694 SK_GEPORT *pPrt;
1695
1696 for (i = 0; i < SK_MAX_MACS; i++) {
1697 pPrt = &pAC->GIni.GP[i];
1698
1699 pPrt->PState = SK_PRT_RESET;
1700 pPrt->PRxQOff = QOffTab[i].RxQOff;
1701 pPrt->PXsQOff = QOffTab[i].XsQOff;
1702 pPrt->PXaQOff = QOffTab[i].XaQOff;
1703 pPrt->PCheckPar = SK_FALSE;
1704 pPrt->PIsave = 0;
1705 pPrt->PPrevShorts = 0;
1706 pPrt->PLinkResCt = 0;
1707 pPrt->PAutoNegTOCt = 0;
1708 pPrt->PPrevRx = 0;
1709 pPrt->PPrevFcs = 0;
1710 pPrt->PRxLim = SK_DEF_RX_WA_LIM;
1711 pPrt->PLinkMode = SK_LMODE_AUTOFULL;
1712 pPrt->PLinkSpeedCap = SK_LSPEED_CAP_1000MBPS;
1713 pPrt->PLinkSpeed = SK_LSPEED_1000MBPS;
1714 pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_UNKNOWN;
1715 pPrt->PLinkModeConf = SK_LMODE_AUTOSENSE;
1716 pPrt->PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
1717 pPrt->PLinkBroken = SK_TRUE; /* See WA code */
1718 pPrt->PLinkCap = (SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL |
1719 SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL);
1720 pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN;
1721 pPrt->PFlowCtrlCap = SK_FLOW_MODE_SYM_OR_REM;
1722 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
1723 pPrt->PMSCap = 0;
1724 pPrt->PMSMode = SK_MS_MODE_AUTO;
1725 pPrt->PMSStatus = SK_MS_STAT_UNSET;
1726 pPrt->PAutoNegFail = SK_FALSE;
1727 pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
1728 pPrt->PHWLinkUp = SK_FALSE;
1729 }
1730
1731 pAC->GIni.GIPortUsage = SK_RED_LINK;
1732
1733} /* SkGeInit0*/
1734
1735#ifdef SK_PCI_RESET
1736
1737/******************************************************************************
1738 *
1739 * SkGePciReset() - Reset PCI interface
1740 *
1741 * Description:
1742 * o Read PCI configuration.
1743 * o Change power state to 3.
1744 * o Change power state to 0.
1745 * o Restore PCI configuration.
1746 *
1747 * Returns:
1748 * 0: Success.
1749 * 1: Power state could not be changed to 3.
1750 */
1751static int SkGePciReset(
1752SK_AC *pAC, /* adapter context */
1753SK_IOC IoC) /* IO context */
1754{
1755 int i;
1756 SK_U16 PmCtlSts;
1757 SK_U32 Bp1;
1758 SK_U32 Bp2;
1759 SK_U16 PciCmd;
1760 SK_U8 Cls;
1761 SK_U8 Lat;
1762 SK_U8 ConfigSpace[PCI_CFG_SIZE];
1763
1764 /*
1765 * Note: Switching to D3 state is like a software reset.
1766 * Switching from D3 to D0 is a hardware reset.
1767 * We have to save and restore the configuration space.
1768 */
1769 for (i = 0; i < PCI_CFG_SIZE; i++) {
1770 SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]);
1771 }
1772
1773 /* We know the RAM Interface Arbiter is enabled. */
1774 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
1775 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1776
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1777 if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {
1778 return(1);
1779 }
1780
1781 /* Return to D0 state. */
1782 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);
1783
1784 /* Check for D0 state. */
1785 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1786
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1787 if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {
1788 return(1);
1789 }
1790
1791 /* Check PCI Config Registers. */
1792 SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
1793 SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
1794 SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
1795 SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2);
1796 SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1797
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1798 if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||
1799 Lat != 0) {
1800 return(1);
1801 }
1802
1803 /* Restore PCI Config Space. */
1804 for (i = 0; i < PCI_CFG_SIZE; i++) {
1805 SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);
1806 }
1807
1808 return(0);
1809} /* SkGePciReset */
1810
1811#endif /* SK_PCI_RESET */
1812
1813/******************************************************************************
1814 *
1815 * SkGeInit1() - Level 1 Initialization
1816 *
1817 * Description:
1818 * o Do a software reset.
1819 * o Clear all reset bits.
1820 * o Verify that the detected hardware is present.
1821 * Return an error if not.
1822 * o Get the hardware configuration
1823 * + Read the number of MACs/Ports.
1824 * + Read the RAM size.
1825 * + Read the PCI Revision Id.
1826 * + Find out the adapters host clock speed
1827 * + Read and check the PHY type
1828 *
1829 * Returns:
1830 * 0: success
1831 * 5: Unexpected PHY type detected
1832 * 6: HW self test failed
1833 */
1834static int SkGeInit1(
1835SK_AC *pAC, /* adapter context */
1836SK_IOC IoC) /* IO context */
1837{
1838 SK_U8 Byte;
1839 SK_U16 Word;
1840 SK_U16 CtrlStat;
1841 SK_U32 FlashAddr;
1842 int RetVal;
1843 int i;
1844
1845 RetVal = 0;
1846
1847 /* save CLK_RUN bits (YUKON-Lite) */
1848 SK_IN16(IoC, B0_CTST, &CtrlStat);
1849
1850#ifdef SK_PCI_RESET
1851 (void)SkGePciReset(pAC, IoC);
1852#endif /* SK_PCI_RESET */
1853
1854 /* do the SW-reset */
1855 SK_OUT8(IoC, B0_CTST, CS_RST_SET);
1856
1857 /* release the SW-reset */
1858 SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
1859
1860 /* reset all error bits in the PCI STATUS register */
1861 /*
1862 * Note: PCI Cfg cycles cannot be used, because they are not
1863 * available on some platforms after 'boot time'.
1864 */
1865 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1866
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1867 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1868 SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
1869 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1870
1871 /* release Master Reset */
1872 SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);
1873
1874#ifdef CLK_RUN
1875 CtrlStat |= CS_CLK_RUN_ENA;
1876#endif /* CLK_RUN */
1877
1878 /* restore CLK_RUN bits */
1879 SK_OUT16(IoC, B0_CTST, CtrlStat &
1880 (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA));
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1881
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1882 /* read Chip Identification Number */
1883 SK_IN8(IoC, B2_CHIP_ID, &Byte);
1884 pAC->GIni.GIChipId = Byte;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1885
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1886 /* read number of MACs */
1887 SK_IN8(IoC, B2_MAC_CFG, &Byte);
1888 pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1889
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1890 /* get Chip Revision Number */
1891 pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4);
1892
1893 /* get diff. PCI parameters */
1894 SK_IN16(IoC, B0_CTST, &CtrlStat);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1895
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1896 /* read the adapters RAM size */
1897 SK_IN8(IoC, B2_E_0, &Byte);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1898
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1899 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
1900
1901 pAC->GIni.GIGenesis = SK_TRUE;
1902
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1903 if (Byte == 3) {
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1904 /* special case: 4 x 64k x 36, offset = 0x80000 */
1905 pAC->GIni.GIRamSize = 1024;
1906 pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
1907 }
1908 else {
1909 pAC->GIni.GIRamSize = (int)Byte * 512;
1910 pAC->GIni.GIRamOffs = 0;
1911 }
1912 /* all GE adapters work with 53.125 MHz host clock */
1913 pAC->GIni.GIHstClkFact = SK_FACT_53;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1914
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1915 /* set Descr. Poll Timer Init Value to 250 ms */
1916 pAC->GIni.GIPollTimerVal =
1917 SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
1918 }
1919 else {
1920 pAC->GIni.GIGenesis = SK_FALSE;
1921
1922#ifndef VCPU
1923 pAC->GIni.GIRamSize = (Byte == 0) ? 128 : (int)Byte * 4;
1924#else
1925 pAC->GIni.GIRamSize = 128;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1926#endif
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1927 pAC->GIni.GIRamOffs = 0;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1928
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1929 /* WA for chip Rev. A */
1930 pAC->GIni.GIWolOffs = (pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1931
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1932 /* get PM Capabilities of PCI config space */
1933 SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word);
1934
1935 /* check if VAUX is available */
1936 if (((CtrlStat & CS_VAUX_AVAIL) != 0) &&
1937 /* check also if PME from D3cold is set */
1938 ((Word & PCI_PME_D3C_SUP) != 0)) {
1939 /* set entry in GE init struct */
1940 pAC->GIni.GIVauxAvail = SK_TRUE;
1941 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1942
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1943 /* save Flash-Address Register */
1944 SK_IN32(IoC, B2_FAR, &FlashAddr);
1945
1946 /* test Flash-Address Register */
1947 SK_OUT8(IoC, B2_FAR + 3, 0xff);
1948 SK_IN8(IoC, B2_FAR + 3, &Byte);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1949
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1950 pAC->GIni.GIYukonLite = (SK_BOOL)(Byte != 0);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1951
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1952 /* restore Flash-Address Register */
1953 SK_OUT32(IoC, B2_FAR, FlashAddr);
1954
1955 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
1956 /* set GMAC Link Control reset */
1957 SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET);
1958
1959 /* clear GMAC Link Control reset */
1960 SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
1961 }
1962 /* all YU chips work with 78.125 MHz host clock */
1963 pAC->GIni.GIHstClkFact = SK_FACT_78;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1964
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1965 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */
1966 }
1967
1968 /* check if 64-bit PCI Slot is present */
1969 pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1970
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1971 /* check if 66 MHz PCI Clock is active */
1972 pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
1973
1974 /* read PCI HW Revision Id. */
1975 SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);
1976 pAC->GIni.GIPciHwRev = Byte;
1977
1978 /* read the PMD type */
1979 SK_IN8(IoC, B2_PMD_TYP, &Byte);
1980 pAC->GIni.GICopperType = (SK_U8)(Byte == 'T');
1981
1982 /* read the PHY type */
1983 SK_IN8(IoC, B2_E_1, &Byte);
1984
1985 Byte &= 0x0f; /* the PHY type is stored in the lower nibble */
1986 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1987
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]1988 if (pAC->GIni.GIGenesis) {
1989 switch (Byte) {
1990 case SK_PHY_XMAC:
1991 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;
1992 break;
1993 case SK_PHY_BCOM:
1994 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;
1995 pAC->GIni.GP[i].PMSCap =
1996 SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE;
1997 break;
1998#ifdef OTHER_PHY
1999 case SK_PHY_LONE:
2000 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;
2001 break;
2002 case SK_PHY_NAT:
2003 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;
2004 break;
2005#endif /* OTHER_PHY */
2006 default:
2007 /* ERROR: unexpected PHY type detected */
2008 RetVal = 5;
2009 break;
2010 }
2011 }
2012 else {
2013 if (Byte == 0) {
2014 /* if this field is not initialized */
2015 Byte = SK_PHY_MARV_COPPER;
2016 pAC->GIni.GICopperType = SK_TRUE;
2017 }
2018 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2019
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2020 if (pAC->GIni.GICopperType) {
2021 pAC->GIni.GP[i].PLinkSpeedCap = SK_LSPEED_CAP_AUTO |
2022 SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS |
2023 SK_LSPEED_CAP_1000MBPS;
2024 pAC->GIni.GP[i].PLinkSpeed = SK_LSPEED_AUTO;
2025 pAC->GIni.GP[i].PMSCap =
2026 SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE;
2027 }
2028 else {
2029 Byte = SK_PHY_MARV_FIBER;
2030 }
2031 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2032
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2033 pAC->GIni.GP[i].PhyType = Byte;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2034
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2035 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
2036 ("PHY type: %d PHY addr: %04x\n", Byte,
2037 pAC->GIni.GP[i].PhyAddr));
2038 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2039
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2040 /* get Mac Type & set function pointers dependent on */
2041 if (pAC->GIni.GIGenesis) {
2042 pAC->GIni.GIMacType = SK_MAC_XMAC;
2043
2044 pAC->GIni.GIFunc.pFnMacUpdateStats = SkXmUpdateStats;
2045 pAC->GIni.GIFunc.pFnMacStatistic = SkXmMacStatistic;
2046 pAC->GIni.GIFunc.pFnMacResetCounter = SkXmResetCounter;
2047 pAC->GIni.GIFunc.pFnMacOverflow = SkXmOverflowStatus;
2048 }
2049 else {
2050 pAC->GIni.GIMacType = SK_MAC_GMAC;
2051
2052 pAC->GIni.GIFunc.pFnMacUpdateStats = SkGmUpdateStats;
2053 pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic;
2054 pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter;
2055 pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2056
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2057#ifdef SPECIAL_HANDLING
2058 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
2059 /* check HW self test result */
2060 SK_IN8(IoC, B2_E_3, &Byte);
2061 if ((Byte & B2_E3_RES_MASK) != 0) {
2062 RetVal = 6;
2063 }
2064 }
2065#endif
2066 }
2067 return(RetVal);
2068} /* SkGeInit1 */
2069
2070
2071/******************************************************************************
2072 *
2073 * SkGeInit2() - Level 2 Initialization
2074 *
2075 * Description:
2076 * - start the Blink Source Counter
2077 * - start the Descriptor Poll Timer
2078 * - configure the MAC-Arbiter
2079 * - configure the Packet-Arbiter
2080 * - enable the Tx Arbiters
2081 * - enable the RAM Interface Arbiter
2082 *
2083 * Returns:
2084 * nothing
2085 */
2086static void SkGeInit2(
2087SK_AC *pAC, /* adapter context */
2088SK_IOC IoC) /* IO context */
2089{
2090 SK_U32 DWord;
2091 int i;
2092
2093 /* start the Descriptor Poll Timer */
2094 if (pAC->GIni.GIPollTimerVal != 0) {
2095 if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) {
2096 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;
2097
2098 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG);
2099 }
2100 SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal);
2101 SK_OUT8(IoC, B28_DPT_CTRL, DPT_START);
2102 }
2103
2104 if (pAC->GIni.GIGenesis) {
2105 /* start the Blink Source Counter */
2106 DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
2107
2108 SK_OUT32(IoC, B2_BSC_INI, DWord);
2109 SK_OUT8(IoC, B2_BSC_CTRL, BSC_START);
2110
2111 /*
2112 * Configure the MAC Arbiter and the Packet Arbiter.
2113 * They will be started once and never be stopped.
2114 */
2115 SkGeInitMacArb(pAC, IoC);
2116
2117 SkGeInitPktArb(pAC, IoC);
2118 }
2119 else {
2120 /* start Time Stamp Timer */
2121 SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START);
2122 }
2123
2124 /* enable the Tx Arbiters */
2125 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
2126 SK_OUT8(IoC, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB);
2127 }
2128
2129 /* enable the RAM Interface Arbiter */
2130 SkGeInitRamIface(pAC, IoC);
2131
2132} /* SkGeInit2 */
2133
2134/******************************************************************************
2135 *
2136 * SkGeInit() - Initialize the GE Adapter with the specified level.
2137 *
2138 * Description:
2139 * Level 0: Initialize the Module structures.
2140 * Level 1: Generic Hardware Initialization. The IOP/MemBase pointer has
2141 * to be set before calling this level.
2142 *
2143 * o Do a software reset.
2144 * o Clear all reset bits.
2145 * o Verify that the detected hardware is present.
2146 * Return an error if not.
2147 * o Get the hardware configuration
2148 * + Set GIMacsFound with the number of MACs.
2149 * + Store the RAM size in GIRamSize.
2150 * + Save the PCI Revision ID in GIPciHwRev.
2151 * o return an error
2152 * if Number of MACs > SK_MAX_MACS
2153 *
2154 * After returning from Level 0 the adapter
2155 * may be accessed with IO operations.
2156 *
2157 * Level 2: start the Blink Source Counter
2158 *
2159 * Returns:
2160 * 0: success
2161 * 1: Number of MACs exceeds SK_MAX_MACS (after level 1)
2162 * 2: Adapter not present or not accessible
2163 * 3: Illegal initialization level
2164 * 4: Initialization Level 1 Call missing
2165 * 5: Unexpected PHY type detected
2166 * 6: HW self test failed
2167 */
2168int SkGeInit(
2169SK_AC *pAC, /* adapter context */
2170SK_IOC IoC, /* IO context */
2171int Level) /* initialization level */
2172{
2173 int RetVal; /* return value */
2174 SK_U32 DWord;
2175
2176 RetVal = 0;
2177 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
2178 ("SkGeInit(Level %d)\n", Level));
2179
2180 switch (Level) {
2181 case SK_INIT_DATA:
2182 /* Initialization Level 0 */
2183 SkGeInit0(pAC, IoC);
2184 pAC->GIni.GILevel = SK_INIT_DATA;
2185 break;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2186
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2187 case SK_INIT_IO:
2188 /* Initialization Level 1 */
2189 RetVal = SkGeInit1(pAC, IoC);
2190 if (RetVal != 0) {
2191 break;
2192 }
2193
2194 /* check if the adapter seems to be accessible */
2195 SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L);
2196 SK_IN32(IoC, B2_IRQM_INI, &DWord);
2197 SK_OUT32(IoC, B2_IRQM_INI, 0L);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2198
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2199 if (DWord != 0x11335577L) {
2200 RetVal = 2;
2201 break;
2202 }
2203
2204 /* check if the number of GIMacsFound matches SK_MAX_MACS */
2205 if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
2206 RetVal = 1;
2207 break;
2208 }
2209
2210 /* Level 1 successfully passed */
2211 pAC->GIni.GILevel = SK_INIT_IO;
2212 break;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2213
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2214 case SK_INIT_RUN:
2215 /* Initialization Level 2 */
2216 if (pAC->GIni.GILevel != SK_INIT_IO) {
2217#ifndef SK_DIAG
2218 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002, SKERR_HWI_E002MSG);
2219#endif /* !SK_DIAG */
2220 RetVal = 4;
2221 break;
2222 }
2223 SkGeInit2(pAC, IoC);
2224
2225 /* Level 2 successfully passed */
2226 pAC->GIni.GILevel = SK_INIT_RUN;
2227 break;
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2228
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2229 default:
2230 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
2231 RetVal = 3;
2232 break;
2233 }
2234
2235 return(RetVal);
2236} /* SkGeInit */
2237
2238
2239/******************************************************************************
2240 *
2241 * SkGeDeInit() - Deinitialize the adapter
2242 *
2243 * Description:
2244 * All ports of the adapter will be stopped if not already done.
2245 * Do a software reset and switch off all LEDs.
2246 *
2247 * Returns:
2248 * nothing
2249 */
2250void SkGeDeInit(
2251SK_AC *pAC, /* adapter context */
2252SK_IOC IoC) /* IO context */
2253{
2254 int i;
2255 SK_U16 Word;
2256
2257#ifndef VCPU
2258 /* ensure I2C is ready */
2259 SkI2cWaitIrq(pAC, IoC);
2260#endif
2261
2262 /* stop all current transfer activity */
2263 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
2264 if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
2265 pAC->GIni.GP[i].PState != SK_PRT_RESET) {
2266
2267 SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
2268 }
2269 }
2270
2271 /* Reset all bits in the PCI STATUS register */
2272 /*
2273 * Note: PCI Cfg cycles cannot be used, because they are not
2274 * available on some platforms after 'boot time'.
2275 */
2276 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2277
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2278 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2279 SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
2280 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2281
2282 /* do the reset, all LEDs are switched off now */
2283 SK_OUT8(IoC, B0_CTST, CS_RST_SET);
2284} /* SkGeDeInit */
2285
2286
2287/******************************************************************************
2288 *
2289 * SkGeInitPort() Initialize the specified port.
2290 *
2291 * Description:
2292 * PRxQSize, PXSQSize, and PXAQSize has to be
2293 * configured for the specified port before calling this function.
2294 * The descriptor rings has to be initialized too.
2295 *
2296 * o (Re)configure queues of the specified port.
2297 * o configure the MAC of the specified port.
2298 * o put ASIC and MAC(s) in operational mode.
2299 * o initialize Rx/Tx and Sync LED
2300 * o initialize RAM Buffers and MAC FIFOs
2301 *
2302 * The port is ready to connect when returning.
2303 *
2304 * Note:
2305 * The MAC's Rx and Tx state machine is still disabled when returning.
2306 *
2307 * Returns:
2308 * 0: success
2309 * 1: Queue size initialization error. The configured values
2310 * for PRxQSize, PXSQSize, or PXAQSize are invalid for one
2311 * or more queues. The specified port was NOT initialized.
2312 * An error log entry was generated.
2313 * 2: The port has to be stopped before it can be initialized again.
2314 */
2315int SkGeInitPort(
2316SK_AC *pAC, /* adapter context */
2317SK_IOC IoC, /* IO context */
2318int Port) /* Port to configure */
2319{
2320 SK_GEPORT *pPrt;
2321
2322 pPrt = &pAC->GIni.GP[Port];
2323
2324 if (SkGeCheckQSize(pAC, Port) != 0) {
2325 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
2326 return(1);
2327 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2328
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2329 if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
2330 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
2331 return(2);
2332 }
2333
2334 /* configuration ok, initialize the Port now */
2335
2336 if (pAC->GIni.GIGenesis) {
2337 /* initialize Rx, Tx and Link LED */
2338 /*
2339 * If 1000BT Phy needs LED initialization than swap
2340 * LED and XMAC initialization order
2341 */
2342 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
2343 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA);
2344 /* The Link LED is initialized by RLMT or Diagnostics itself */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2345
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2346 SkXmInitMac(pAC, IoC, Port);
2347 }
2348 else {
2349
2350 SkGmInitMac(pAC, IoC, Port);
2351 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2352
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2353 /* do NOT initialize the Link Sync Counter */
2354
2355 SkGeInitMacFifo(pAC, IoC, Port);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2356
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2357 SkGeInitRamBufs(pAC, IoC, Port);
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2358
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2359 if (pPrt->PXSQSize != 0) {
2360 /* enable Force Sync bit if synchronous queue available */
2361 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
2362 }
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2363
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]2364 SkGeInitBmu(pAC, IoC, Port);
2365
2366 /* mark port as initialized */
2367 pPrt->PState = SK_PRT_INIT;
2368
2369 return(0);
2370} /* SkGeInitPort */
wdenk149dded2003-09-10 18:20:28 +0000[diff] [blame]2371
2372#endif /* CONFIG_SK98 */