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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simeke6a9ed02015-11-20 13:17:22 +01002/*
3 * Copyright 2015 - 2016 Xilinx, Inc.
4 *
5 * Michal Simek <michal.simek@xilinx.com>
Michal Simeke6a9ed02015-11-20 13:17:22 +01006 */
7
8#include <common.h>
Simon Glass4d72caa2020-05-10 11:40:01 -06009#include <image.h>
Simon Glass52559322019-11-14 12:57:46 -070010#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Michal Simeke6a9ed02015-11-20 13:17:22 +010012#include <spl.h>
Simon Glassc05ed002020-05-10 11:40:11 -060013#include <linux/delay.h>
Michal Simeke6a9ed02015-11-20 13:17:22 +010014
15#include <asm/io.h>
16#include <asm/spl.h>
17#include <asm/arch/hardware.h>
Michal Simeke82024d2019-12-03 15:02:50 +010018#include <asm/arch/psu_init_gpl.h>
Michal Simeke6a9ed02015-11-20 13:17:22 +010019#include <asm/arch/sys_proto.h>
20
21void board_init_f(ulong dummy)
22{
Michal Simek55de0922017-07-12 13:08:41 +020023 board_early_init_f();
Michal Simeke6a9ed02015-11-20 13:17:22 +010024 board_early_init_r();
Michal Simeke6a9ed02015-11-20 13:17:22 +010025}
26
Michal Simek48255f52016-08-15 09:41:36 +020027static void ps_mode_reset(ulong mode)
28{
Michal Simek48255f52016-08-15 09:41:36 +020029 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
30 &crlapb_base->boot_pin_ctrl);
31 udelay(5);
32 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
33 mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
34 &crlapb_base->boot_pin_ctrl);
35}
36
37/*
38 * Set default PS_MODE1 which is used for USB ULPI phy reset
39 * Also other resets can be connected to this certain pin
40 */
41#ifndef MODE_RESET
42# define MODE_RESET PS_MODE1
43#endif
44
Michal Simeke6a9ed02015-11-20 13:17:22 +010045#ifdef CONFIG_SPL_BOARD_INIT
46void spl_board_init(void)
47{
48 preloader_console_init();
Michal Simek48255f52016-08-15 09:41:36 +020049 ps_mode_reset(MODE_RESET);
Michal Simeke6a9ed02015-11-20 13:17:22 +010050 board_init();
Michal Simeke82024d2019-12-03 15:02:50 +010051 psu_post_config_data();
Michal Simeke6a9ed02015-11-20 13:17:22 +010052}
53#endif
54
Michal Simekde79ca952019-12-09 13:00:57 +010055void board_boot_order(u32 *spl_boot_list)
56{
57 spl_boot_list[0] = spl_boot_device();
58
59 if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
60 spl_boot_list[1] = BOOT_DEVICE_MMC2;
61 if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
62 spl_boot_list[1] = BOOT_DEVICE_MMC1;
Michal Simekf1433d02020-03-11 15:00:51 +010063
64 spl_boot_list[2] = BOOT_DEVICE_RAM;
Michal Simekde79ca952019-12-09 13:00:57 +010065}
66
Michal Simeke6a9ed02015-11-20 13:17:22 +010067u32 spl_boot_device(void)
68{
69 u32 reg = 0;
70 u8 bootmode;
71
Michal Simek7f491d72016-08-30 16:17:27 +020072#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
73 /* Change default boot mode at run-time */
Michal Simek47359a02016-10-25 11:43:02 +020074 writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
Michal Simek7f491d72016-08-30 16:17:27 +020075 &crlapb_base->boot_mode);
76#endif
77
Michal Simeke6a9ed02015-11-20 13:17:22 +010078 reg = readl(&crlapb_base->boot_mode);
Michal Simek47359a02016-10-25 11:43:02 +020079 if (reg >> BOOT_MODE_ALT_SHIFT)
80 reg >>= BOOT_MODE_ALT_SHIFT;
81
Michal Simeke6a9ed02015-11-20 13:17:22 +010082 bootmode = reg & BOOT_MODES_MASK;
83
84 switch (bootmode) {
85 case JTAG_MODE:
86 return BOOT_DEVICE_RAM;
87#ifdef CONFIG_SPL_MMC_SUPPORT
Michal Simeke6a9ed02015-11-20 13:17:22 +010088 case SD_MODE1:
Michal Simekb0259c82017-03-02 11:02:55 +010089 case SD1_LSHFT_MODE: /* not working on silicon v1 */
Jean-Francois Dagenaise3fdf5d2017-04-02 21:44:34 -040090 return BOOT_DEVICE_MMC2;
Jean-Francois Dagenaise3fdf5d2017-04-02 21:44:34 -040091 case SD_MODE:
92 case EMMC_MODE:
Michal Simeke6a9ed02015-11-20 13:17:22 +010093 return BOOT_DEVICE_MMC1;
94#endif
Andrew F. Davis6536ca42019-01-17 13:43:02 -060095#ifdef CONFIG_SPL_DFU
Michal Simekd58fc122016-08-19 14:14:52 +020096 case USB_MODE:
97 return BOOT_DEVICE_DFU;
98#endif
Michal Simek26610812016-10-26 09:24:32 +020099#ifdef CONFIG_SPL_SATA_SUPPORT
100 case SW_SATA_MODE:
101 return BOOT_DEVICE_SATA;
102#endif
Michal Simek40d1f8a2017-11-02 09:15:05 +0100103#ifdef CONFIG_SPL_SPI_SUPPORT
104 case QSPI_MODE_24BIT:
105 case QSPI_MODE_32BIT:
106 return BOOT_DEVICE_SPI;
107#endif
Michal Simeke6a9ed02015-11-20 13:17:22 +0100108 default:
109 printf("Invalid Boot Mode:0x%x\n", bootmode);
110 break;
111 }
112
113 return 0;
114}
115
Michal Simeke6a9ed02015-11-20 13:17:22 +0100116#ifdef CONFIG_SPL_OS_BOOT
117int spl_start_uboot(void)
118{
Michal Simeke6a9ed02015-11-20 13:17:22 +0100119 return 0;
120}
121#endif
122
123#ifdef CONFIG_SPL_LOAD_FIT
124int board_fit_config_name_match(const char *name)
125{
126 /* Just empty function now - can't decide what to choose */
127 debug("%s: %s\n", __func__, name);
128
Michal Simekb4f84682019-12-09 08:39:19 +0100129 return -1;
Michal Simeke6a9ed02015-11-20 13:17:22 +0100130}
131#endif