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wdenk1eaeb582004-06-08 00:22:43 +00001/*
2 * Board specific setup info
3 *
4 * (C) Copyright 2003
5 * Texas Instruments, <www.ti.com>
6 * Kshitij Gupta <Kshitij@ti.com>
7 *
8 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
9 *
10 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <config.h>
31#include <version.h>
32
33#if defined(CONFIG_OMAP1610)
34#include <./configs/omap1510.h>
35#endif
36
37
38_TEXT_BASE:
39 .word TEXT_BASE /* sdram load addr from config.mk */
40
41.globl platformsetup
42platformsetup:
43
44
45 /*------------------------------------------------------*
46 *mask all IRQs by setting all bits in the INTMR default*
47 *------------------------------------------------------*/
48 mov r1, #0xffffffff
49 ldr r0, =REG_IHL1_MIR
50 str r1, [r0]
51 ldr r0, =REG_IHL2_MIR
52 str r1, [r0]
53
54 /*------------------------------------------------------*
55 * Set up ARM CLM registers (IDLECT1) *
56 *------------------------------------------------------*/
57 ldr r0, REG_ARM_IDLECT1
58 ldr r1, VAL_ARM_IDLECT1
59 str r1, [r0]
60
61 /*------------------------------------------------------*
62 * Set up ARM CLM registers (IDLECT2) *
63 *------------------------------------------------------*/
64 ldr r0, REG_ARM_IDLECT2
65 ldr r1, VAL_ARM_IDLECT2
66 str r1, [r0]
67
68 /*------------------------------------------------------*
69 * Set up ARM CLM registers (IDLECT3) *
70 *------------------------------------------------------*/
71 ldr r0, REG_ARM_IDLECT3
72 ldr r1, VAL_ARM_IDLECT3
73 str r1, [r0]
74
75
76 mov r1, #0x01 /* PER_EN bit */
77 ldr r0, REG_ARM_RSTCT2
78 strh r1, [r0] /* CLKM; Peripheral reset. */
79
80 /* Set CLKM to Sync-Scalable */
81 /* I supposedly need to enable the dsp clock before switching */
82 mov r1, #0x0000
83 ldr r0, REG_ARM_SYSST
84 strh r1, [r0]
85 mov r0, #0x400
861:
87 subs r0, r0, #0x1 /* wait for any bubbles to finish */
88 bne 1b
89 ldr r1, VAL_ARM_CKCTL
90 ldr r0, REG_ARM_CKCTL
91 strh r1, [r0]
92
93 /* a few nops to let settle */
94 nop
95 nop
96 nop
97 nop
98 nop
99 nop
100 nop
101 nop
102 nop
103 nop
104
105 /* setup DPLL 1 */
106 /* Ramp up the clock to 96Mhz */
107 ldr r1, VAL_DPLL1_CTL
108 ldr r0, REG_DPLL1_CTL
109 strh r1, [r0]
110 ands r1, r1, #0x10 /* Check if PLL is enabled. */
111 beq lock_end /* Do not look for lock if BYPASS selected */
1122:
113 ldrh r1, [r0]
114 ands r1, r1, #0x01 /* Check the LOCK bit.*/
115 beq 2b /* loop until bit goes hi. */
116lock_end:
117
118
119 /*------------------------------------------------------*
120 * Turn off the watchdog during init... *
121 *------------------------------------------------------*/
122 ldr r0, REG_WATCHDOG
123 ldr r1, WATCHDOG_VAL1
124 str r1, [r0]
125 ldr r1, WATCHDOG_VAL2
126 str r1, [r0]
127 ldr r0, REG_WSPRDOG
128 ldr r1, WSPRDOG_VAL1
129 str r1, [r0]
130 ldr r0, REG_WWPSDOG
131
132watch1Wait:
133 ldr r1, [r0]
134 tst r1, #0x10
135 bne watch1Wait
136
137 ldr r0, REG_WSPRDOG
138 ldr r1, WSPRDOG_VAL2
139 str r1, [r0]
140 ldr r0, REG_WWPSDOG
141watch2Wait:
142 ldr r1, [r0]
143 tst r1, #0x10
144 bne watch2Wait
145
146
147 /* Set memory timings corresponding to the new clock speed */
148
149 /* Check execution location to determine current execution location
150 * and branch to appropriate initialization code.
151 */
152 /* Load physical SDRAM base. */
153 mov r0, #0x10000000
154 /* Get current execution location. */
155 mov r1, pc
156 /* Compare. */
157 cmp r1, r0
158 /* Skip over EMIF-fast initialization if running from SDRAM. */
159 bge skip_sdram
160
161 /*
162 * Delay for SDRAM initialization.
163 */
164 mov r3, #0x1800 /* value should be checked */
1653:
166 subs r3, r3, #0x1 /* Decrement count */
167 bne 3b
168
169
170 /*
171 * Set SDRAM control values. Disable refresh before MRS command.
172 */
173
174 /* mobile ddr operation */
175 ldr r0, REG_SDRAM_OPERATION
176 mov r2, #07
177 str r2, [r0]
178
179 /* config register */
180 ldr r0, REG_SDRAM_CONFIG
181 ldr r1, SDRAM_CONFIG_VAL
182 str r1, [r0]
183
184 /* manual command register */
185 ldr r0, REG_SDRAM_MANUAL_CMD
186 /* issue set cke high */
187 mov r1, #CMD_SDRAM_CKE_SET_HIGH
188 str r1, [r0]
189 /* issue nop */
190 mov r1, #CMD_SDRAM_NOP
191 str r1, [r0]
192
193 mov r2, #0x0100
194waitMDDR1:
195 subs r2, r2, #1
196 bne waitMDDR1 /* delay loop */
197
198 /* issue precharge */
199 mov r1, #CMD_SDRAM_PRECHARGE
200 str r1, [r0]
201
202 /* issue autorefresh x 2 */
203 mov r1, #CMD_SDRAM_AUTOREFRESH
204 str r1, [r0]
205 str r1, [r0]
206
207 /* mrs register ddr mobile */
208 ldr r0, REG_SDRAM_MRS
209 mov r1, #0x33
210 str r1, [r0]
211
212 /* emrs1 low-power register */
213 ldr r0, REG_SDRAM_EMRS1
214 /* self refresh on all banks */
215 mov r1, #0
216 str r1, [r0]
217
218 ldr r0, REG_DLL_URD_CONTROL
219 ldr r1, DLL_URD_CONTROL_VAL
220 str r1, [r0]
221
222 ldr r0, REG_DLL_LRD_CONTROL
223 ldr r1, DLL_LRD_CONTROL_VAL
224 str r1, [r0]
225
226 ldr r0, REG_DLL_WRT_CONTROL
227 ldr r1, DLL_WRT_CONTROL_VAL
228 str r1, [r0]
229
230 /* delay loop */
231 mov r2, #0x0100
232waitMDDR2:
233 subs r2, r2, #1
234 bne waitMDDR2
235
236 /*
237 * Delay for SDRAM initialization.
238 */
239 mov r3, #0x1800
2404:
241 subs r3, r3, #1 /* Decrement count. */
242 bne 4b
243 b common_tc
244
245skip_sdram:
246
247 ldr r0, REG_SDRAM_CONFIG
248 ldr r1, SDRAM_CONFIG_VAL
249 str r1, [r0]
250
251common_tc:
252 /* slow interface */
253 ldr r1, VAL_TC_EMIFS_CS0_CONFIG
254 ldr r0, REG_TC_EMIFS_CS0_CONFIG
255 str r1, [r0] /* Chip Select 0 */
256
257 ldr r1, VAL_TC_EMIFS_CS1_CONFIG
258 ldr r0, REG_TC_EMIFS_CS1_CONFIG
259 str r1, [r0] /* Chip Select 1 */
260 ldr r1, VAL_TC_EMIFS_CS3_CONFIG
261 ldr r0, REG_TC_EMIFS_CS3_CONFIG
262 str r1, [r0] /* Chip Select 3 */
263
264#ifdef CONFIG_H2_OMAP1610
265 /* inserting additional 2 clock cycle hold time for LAN */
266 ldr r0, REG_TC_EMIFS_CS1_ADVANCED
267 ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
268 str r1, [r0]
269#endif
270 /* Start MPU Timer 1 */
271 ldr r0, REG_MPU_LOAD_TIMER
272 ldr r1, VAL_MPU_LOAD_TIMER
273 str r1, [r0]
274
275 ldr r0, REG_MPU_CNTL_TIMER
276 ldr r1, VAL_MPU_CNTL_TIMER
277 str r1, [r0]
278
279 /* back to arch calling code */
280 mov pc, lr
281
282 /* the literal pools origin */
283 .ltorg
284
285
286REG_TC_EMIFS_CONFIG: /* 32 bits */
287 .word 0xfffecc0c
288REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
289 .word 0xfffecc10
290REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
291 .word 0xfffecc14
292REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
293 .word 0xfffecc18
294REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
295 .word 0xfffecc1c
296
297#ifdef CONFIG_H2_OMAP1610
298REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
299 .word 0xfffecc54
300#endif
301
302/* MPU clock/reset/power mode control registers */
303REG_ARM_CKCTL: /* 16 bits */
304 .word 0xfffece00
305
306REG_ARM_IDLECT3: /* 16 bits */
307 .word 0xfffece24
308REG_ARM_IDLECT2: /* 16 bits */
309 .word 0xfffece08
310REG_ARM_IDLECT1: /* 16 bits */
311 .word 0xfffece04
312
313REG_ARM_RSTCT2: /* 16 bits */
314 .word 0xfffece14
315REG_ARM_SYSST: /* 16 bits */
316 .word 0xfffece18
317/* DPLL control registers */
318REG_DPLL1_CTL: /* 16 bits */
319 .word 0xfffecf00
320
321/* Watch Dog register */
322/* secure watchdog stop */
323REG_WSPRDOG:
324 .word 0xfffeb048
325/* watchdog write pending */
326REG_WWPSDOG:
327 .word 0xfffeb034
328
329WSPRDOG_VAL1:
330 .word 0x0000aaaa
331WSPRDOG_VAL2:
332 .word 0x00005555
333
334/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
335 counter @8192 rows, 10 ns, 8 burst */
336REG_SDRAM_CONFIG:
337 .word 0xfffecc20
338
339/* Operation register */
340REG_SDRAM_OPERATION:
341 .word 0xfffecc80
342
343/* Manual command register */
344REG_SDRAM_MANUAL_CMD:
345 .word 0xfffecc84
346
347/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
348REG_SDRAM_MRS:
349 .word 0xfffecc70
350
351/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
352REG_SDRAM_EMRS1:
353 .word 0xfffecc78
354
355/* WRT DLL register */
356REG_DLL_WRT_CONTROL:
357 .word 0xfffecc68
358DLL_WRT_CONTROL_VAL:
359 .word 0x03f00002
360
361/* URD DLL register */
362REG_DLL_URD_CONTROL:
363 .word 0xfffeccc0
364DLL_URD_CONTROL_VAL:
365 .word 0x00800002
366
367/* LRD DLL register */
368REG_DLL_LRD_CONTROL:
369 .word 0xfffecccc
370
371REG_WATCHDOG:
372 .word 0xfffec808
373
374REG_MPU_LOAD_TIMER:
375 .word 0xfffec600
376REG_MPU_CNTL_TIMER:
377 .word 0xfffec500
378
379/* 96 MHz Samsung Mobile DDR */
380SDRAM_CONFIG_VAL:
381 .word 0x001200f4
382
383DLL_LRD_CONTROL_VAL:
384 .word 0x00800002
385
386VAL_ARM_CKCTL:
387 .word 0x3000
388VAL_DPLL1_CTL:
389 .word 0x2830
390
391#ifdef CONFIG_OSK_OMAP5912
392VAL_TC_EMIFS_CS0_CONFIG:
393 .word 0x002130b0
394VAL_TC_EMIFS_CS1_CONFIG:
395 .word 0x00001131
396VAL_TC_EMIFS_CS2_CONFIG:
397 .word 0x000055f0
398VAL_TC_EMIFS_CS3_CONFIG:
399 .word 0x88011131
400#endif
401
402#ifdef CONFIG_H2_OMAP1610
403VAL_TC_EMIFS_CS0_CONFIG:
404 .word 0x00203331
405VAL_TC_EMIFS_CS1_CONFIG:
406 .word 0x8180fff3
407VAL_TC_EMIFS_CS2_CONFIG:
408 .word 0xf800f22a
409VAL_TC_EMIFS_CS3_CONFIG:
410 .word 0x88011131
411VAL_TC_EMIFS_CS1_ADVANCED:
412 .word 0x00000022
413#endif
414
415VAL_TC_EMIFF_SDRAM_CONFIG:
416 .word 0x010290fc
417VAL_TC_EMIFF_MRS:
418 .word 0x00000027
419
420VAL_ARM_IDLECT1:
421 .word 0x00000400
422
423VAL_ARM_IDLECT2:
424 .word 0x00000886
425VAL_ARM_IDLECT3:
426 .word 0x00000015
427
428WATCHDOG_VAL1:
429 .word 0x000000f5
430WATCHDOG_VAL2:
431 .word 0x000000a0
432
433VAL_MPU_LOAD_TIMER:
434 .word 0xffffffff
435VAL_MPU_CNTL_TIMER:
436 .word 0xffffffa1
437
438/* command values */
439.equ CMD_SDRAM_NOP, 0x00000000
440.equ CMD_SDRAM_PRECHARGE, 0x00000001
441.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
442.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007