blob: 233bee002d0059ed910192f5265b8f0f92388f80 [file] [log] [blame]
Heiko Schocherac9db062008-01-11 01:12:08 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC8247 1
33#define CONFIG_MPC8272_FAMILY 1
34#define CONFIG_MGCOGE 1
35
36#define CONFIG_CPM2 1 /* Has a CPM2 */
37
Heiko Schocher1e8f4e72008-11-20 09:59:09 +010038/* include common defines/options for all Keymile boards */
39#include "keymile-common.h"
Heiko Schochere492c902008-03-07 08:13:41 +010040
Heiko Schocherac9db062008-01-11 01:12:08 +010041/*
42 * Select serial console configuration
43 *
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
46 * for SCC).
47 */
48#define CONFIG_CONS_ON_SMC /* Console is on SMC */
49#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50#undef CONFIG_CONS_NONE /* It's not on external UART */
51#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
52
53/*
54 * Select ethernet configuration
55 *
56 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
57 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
58 * SCC, 1-3 for FCC)
59 *
60 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
61 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
62 * must be unset.
63 */
64#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
65#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
66#undef CONFIG_ETHER_NONE /* No external Ethernet */
67
68#define CONFIG_ETHER_INDEX 4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
Heiko Schocherac9db062008-01-11 01:12:08 +010070
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
Heiko Schocherac9db062008-01-11 01:12:08 +010072
73#ifndef CONFIG_8260_CLKIN
74#define CONFIG_8260_CLKIN 66000000 /* in Hz */
75#endif
76
Heiko Schocherac9db062008-01-11 01:12:08 +010077/*
78 * Default environment settings
79 */
Detlev Zundelc61e0332008-04-03 14:18:48 +020080#define CONFIG_EXTRA_ENV_SETTINGS \
81 "netdev=eth0\0" \
82 "u-boot_addr=100000\0" \
83 "kernel_addr=200000\0" \
84 "fdt_addr=400000\0" \
85 "rootpath=/opt/eldk-4.2/ppc_82xx\0" \
86 "u-boot=/tftpboot/mgcoge/u-boot.bin\0" \
87 "bootfile=/tftpboot/mgcoge/uImage\0" \
88 "fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0" \
89 "load=tftp ${u-boot_addr} ${u-boot}\0" \
90 "update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; " \
91 "cp.b ${u-boot_addr} fe000000 ${filesize};" \
92 "prot on fe000000 fe03ffff\0" \
93 "ramargs=setenv bootargs root=/dev/ram rw\0" \
94 "nfsargs=setenv bootargs root=/dev/nfs rw " \
95 "nfsroot=${serverip}:${rootpath}\0" \
Detlev Zundelf3085722008-04-03 14:18:47 +020096 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
Detlev Zundelc61e0332008-04-03 14:18:48 +020097 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
98 "addip=setenv bootargs ${bootargs} " \
99 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
100 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
101 "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
102 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
103 "bootm ${kernel_addr} - ${fdt_addr}\0" \
104 "net_self=tftp ${kernel_addr} ${bootfile}; " \
105 "tftp ${fdt_addr} ${fdt_file}; " \
106 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
107 "run ramargs addip; " \
108 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Heiko Schocherac9db062008-01-11 01:12:08 +0100109 ""
Heiko Schocherac9db062008-01-11 01:12:08 +0100110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_SDRAM_BASE 0x00000000
112#define CONFIG_SYS_FLASH_BASE 0xFE000000
113#define CONFIG_SYS_FLASH_SIZE 32
114#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200115#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
117#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
Heiko Schochere492c902008-03-07 08:13:41 +0100118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_FLASH_BASE_1 0x50000000
120#define CONFIG_SYS_FLASH_SIZE_1 64
Heiko Schochere492c902008-03-07 08:13:41 +0100121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
Heiko Schocherac9db062008-01-11 01:12:08 +0100123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
125#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
126#define CONFIG_SYS_RAMBOOT
Heiko Schocherac9db062008-01-11 01:12:08 +0100127#endif
128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
Heiko Schocherac9db062008-01-11 01:12:08 +0100130
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200131#define CONFIG_ENV_IS_IN_FLASH
Heiko Schocherac9db062008-01-11 01:12:08 +0100132
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200133#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200134#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Heiko Schocher360fe712008-10-17 18:24:06 +0200136#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
137
138/* Address and size of Redundant Environment Sector */
139#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
140#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200141#endif /* CONFIG_ENV_IS_IN_FLASH */
Heiko Schocherac9db062008-01-11 01:12:08 +0100142
Heiko Schocher9661bf92008-10-15 09:36:03 +0200143/* enable I2C and select the hardware/software driver */
144#undef CONFIG_HARD_I2C /* I2C with hardware support */
145#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
147#define CONFIG_SYS_I2C_SLAVE 0x7F
Heiko Schocher9661bf92008-10-15 09:36:03 +0200148
149/*
150 * Software (bit-bang) I2C driver configuration
151 */
152
153#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
154#define I2C_ACTIVE (iop->pdir |= 0x00010000)
155#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
156#define I2C_READ ((iop->pdat & 0x00010000) != 0)
157#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
158 else iop->pdat &= ~0x00010000
159#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
160 else iop->pdat &= ~0x00020000
161#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
162
163#define CONFIG_I2C_MULTI_BUS 1
164#define CONFIG_I2C_CMD_TREE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_MAX_I2C_BUS 2
166#define CONFIG_SYS_I2C_INIT_BOARD 1
Heiko Schocher67b23a32008-10-15 09:39:47 +0200167#define CONFIG_I2C_MUX 1
Heiko Schocher9661bf92008-10-15 09:36:03 +0200168
Heiko Schocherf2202452008-10-15 09:36:33 +0200169/* EEprom support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
171#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
172#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
173#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
174#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Heiko Schocherf2202452008-10-15 09:36:33 +0200175
Heiko Schocher8f64da72008-10-15 09:41:00 +0200176/* Support the IVM EEprom */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_IVM_EEPROM_ADR 0x50
178#define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
179#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
Heiko Schocher8f64da72008-10-15 09:41:00 +0200180
Heiko Schochere5e4edd2008-10-15 09:38:07 +0200181/* I2C SYSMON (LM75, AD7414 is almost compatible) */
182#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
183#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_DTT_MAX_TEMP 70
185#define CONFIG_SYS_DTT_LOW_TEMP -30
186#define CONFIG_SYS_DTT_HYSTERESIS 3
187#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
Heiko Schochere5e4edd2008-10-15 09:38:07 +0200188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_IMMR 0xF0000000
Heiko Schocherac9db062008-01-11 01:12:08 +0100190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
192#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
193#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
194#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
195#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocherac9db062008-01-11 01:12:08 +0100196
197/* Hard reset configuration word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_HRCW_MASTER 0x0604b211
Heiko Schocherac9db062008-01-11 01:12:08 +0100199
200/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_HRCW_SLAVE1 0
202#define CONFIG_SYS_HRCW_SLAVE2 0
203#define CONFIG_SYS_HRCW_SLAVE3 0
204#define CONFIG_SYS_HRCW_SLAVE4 0
205#define CONFIG_SYS_HRCW_SLAVE5 0
206#define CONFIG_SYS_HRCW_SLAVE6 0
207#define CONFIG_SYS_HRCW_SLAVE7 0
Heiko Schocherac9db062008-01-11 01:12:08 +0100208
209#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
210#define BOOTFLAG_WARM 0x02 /* Software reboot */
211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
213#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocherac9db062008-01-11 01:12:08 +0100214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
Heiko Schocherac9db062008-01-11 01:12:08 +0100216#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Heiko Schocherac9db062008-01-11 01:12:08 +0100218#endif
219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_HID0_INIT 0
221#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
Heiko Schocherac9db062008-01-11 01:12:08 +0100222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_HID2 0
Heiko Schocherac9db062008-01-11 01:12:08 +0100224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_SIUMCR 0x4020c200
226#define CONFIG_SYS_SYPCR 0xFFFFFFC3
227#define CONFIG_SYS_BCR 0x10000000
228#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
Heiko Schocherac9db062008-01-11 01:12:08 +0100229
230/*-----------------------------------------------------------------------
231 * RMR - Reset Mode Register 5-5
232 *-----------------------------------------------------------------------
233 * turn on Checkstop Reset Enable
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_RMR 0
Heiko Schocherac9db062008-01-11 01:12:08 +0100236
237/*-----------------------------------------------------------------------
238 * TMCNTSC - Time Counter Status and Control 4-40
239 *-----------------------------------------------------------------------
240 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
241 * and enable Time Counter
242 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
Heiko Schocherac9db062008-01-11 01:12:08 +0100244
245/*-----------------------------------------------------------------------
246 * PISCR - Periodic Interrupt Status and Control 4-42
247 *-----------------------------------------------------------------------
248 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
249 * Periodic timer
250 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
Heiko Schocherac9db062008-01-11 01:12:08 +0100252
253/*-----------------------------------------------------------------------
254 * RCCR - RISC Controller Configuration 13-7
255 *-----------------------------------------------------------------------
256 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_RCCR 0
Heiko Schocherac9db062008-01-11 01:12:08 +0100258
259/*
260 * Init Memory Controller:
261 *
262 * Bank Bus Machine PortSz Device
263 * ---- --- ------- ------ ------
264 * 0 60x GPCM 8 bit FLASH
265 * 1 60x SDRAM 32 bit SDRAM
Heiko Schochere492c902008-03-07 08:13:41 +0100266 * 3 60x GPCM 8 bit GPIO/PIGGY
267 * 5 60x GPCM 16 bit CFG-Flash
Heiko Schocherac9db062008-01-11 01:12:08 +0100268 *
269 */
270/* Bank 0 - FLASH
271 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
Heiko Schocherac9db062008-01-11 01:12:08 +0100273 BRx_PS_8 |\
274 BRx_MS_GPCM_P |\
275 BRx_V)
276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
Heiko Schocherac9db062008-01-11 01:12:08 +0100278 ORxG_CSNT |\
279 ORxG_ACS_DIV2 |\
280 ORxG_SCY_5_CLK |\
281 ORxG_TRLX )
282
283
284/* Bank 1 - 60x bus SDRAM
285 */
286#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
Heiko Schocherac9db062008-01-11 01:12:08 +0100288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_MPTPR 0x1800
Heiko Schocherac9db062008-01-11 01:12:08 +0100290
291/*-----------------------------------------------------------------------------
292 * Address for Mode Register Set (MRS) command
293 *-----------------------------------------------------------------------------
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_MRS_OFFS 0x00000110
296#define CONFIG_SYS_PSRT 0x0e
Heiko Schocherac9db062008-01-11 01:12:08 +0100297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
Heiko Schocherac9db062008-01-11 01:12:08 +0100299 BRx_PS_64 |\
300 BRx_MS_SDRAM_P |\
301 BRx_V)
302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
Heiko Schocherac9db062008-01-11 01:12:08 +0100304
305/* SDRAM initialization values
306*/
307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocherac9db062008-01-11 01:12:08 +0100309 ORxS_BPD_8 |\
310 ORxS_ROWST_PBI0_A7 |\
311 ORxS_NUMR_13)
312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
Heiko Schocherac9db062008-01-11 01:12:08 +0100314 PSDMR_BSMA_A14_A16 |\
315 PSDMR_SDA10_PBI0_A9 |\
316 PSDMR_RFRC_5_CLK |\
317 PSDMR_PRETOACT_2W |\
318 PSDMR_ACTTORW_2W |\
319 PSDMR_LDOTOPRE_1C |\
320 PSDMR_WRC_1C |\
321 PSDMR_CL_2)
322
Heiko Schochere492c902008-03-07 08:13:41 +0100323/* GPIO/PIGGY on CS3 initialization values
324*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_PIGGY_BASE 0x30000000
326#define CONFIG_SYS_PIGGY_SIZE 128
Heiko Schochere492c902008-03-07 08:13:41 +0100327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
Heiko Schochere492c902008-03-07 08:13:41 +0100329 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
Heiko Schochere492c902008-03-07 08:13:41 +0100332 ORxG_CSNT | ORxG_ACS_DIV2 |\
333 ORxG_SCY_3_CLK | ORxG_TRLX )
334
335/* CFG-Flash on CS5 initialization values
336*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
Heiko Schochere492c902008-03-07 08:13:41 +0100338 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1) |\
Heiko Schochere492c902008-03-07 08:13:41 +0100341 ORxG_CSNT | ORxG_ACS_DIV2 |\
342 ORxG_SCY_5_CLK | ORxG_TRLX )
343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
Heiko Schocherac9db062008-01-11 01:12:08 +0100345
346/* pass open firmware flat tree */
Heiko Schochere02d4a92008-10-16 16:32:35 +0200347#define CONFIG_FIT 1
Heiko Schocherac9db062008-01-11 01:12:08 +0100348#define CONFIG_OF_LIBFDT 1
349#define CONFIG_OF_BOARD_SETUP 1
350
351#define OF_CPU "PowerPC,8247@0"
352#define OF_SOC "soc@f0000000"
353#define OF_TBCLK (bd->bi_busfreq / 4)
354#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
355
Heiko Schocherac9db062008-01-11 01:12:08 +0100356#endif /* __CONFIG_H */