| Chris Zankel | c978b52 | 2016-08-10 18:36:44 +0300 | [diff] [blame] | 1 | menu "Xtensa architecture" |
| 2 | depends on XTENSA |
| 3 | |
| 4 | config SYS_ARCH |
| 5 | string |
| 6 | default "xtensa" |
| 7 | |
| 8 | config SYS_CPU |
| 9 | string "Xtensa Core Variant" |
| 10 | |
| 11 | choice |
| 12 | prompt "Target select" |
| 13 | |
| Chris Zankel | 7e270ec | 2016-08-10 18:36:48 +0300 | [diff] [blame] | 14 | config TARGET_XTFPGA |
| 15 | bool "Support XTFPGA" |
| Tom Rini | 6d21dd3 | 2022-02-25 11:19:47 -0500 | [diff] [blame] | 16 | select BOARD_POSTCLK_INIT |
| Chris Zankel | c978b52 | 2016-08-10 18:36:44 +0300 | [diff] [blame] | 17 | |
| Jiaxun Yang | 206ad6c | 2024-06-18 14:56:09 +0100 | [diff] [blame] | 18 | config TARGET_QEMU_XTENSA |
| 19 | bool "Support QEMU Xtensa Virt Board" |
| 20 | select BOARD_LATE_INIT |
| 21 | |
| Chris Zankel | c978b52 | 2016-08-10 18:36:44 +0300 | [diff] [blame] | 22 | endchoice |
| 23 | |
| Trevor Woerner | a0aba8a | 2019-05-03 09:40:59 -0400 | [diff] [blame] | 24 | config SYS_ICACHE_OFF |
| 25 | bool "Do not enable icache" |
| Trevor Woerner | a0aba8a | 2019-05-03 09:40:59 -0400 | [diff] [blame] | 26 | help |
| 27 | Do not enable instruction cache in U-Boot. |
| 28 | |
| Trevor Woerner | 1001502 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 29 | config SPL_SYS_ICACHE_OFF |
| 30 | bool "Do not enable icache in SPL" |
| 31 | depends on SPL |
| 32 | default SYS_ICACHE_OFF |
| 33 | help |
| 34 | Do not enable instruction cache in SPL. |
| 35 | |
| Trevor Woerner | a0aba8a | 2019-05-03 09:40:59 -0400 | [diff] [blame] | 36 | config SYS_DCACHE_OFF |
| 37 | bool "Do not enable dcache" |
| Trevor Woerner | a0aba8a | 2019-05-03 09:40:59 -0400 | [diff] [blame] | 38 | help |
| 39 | Do not enable data cache in U-Boot. |
| 40 | |
| Trevor Woerner | 1001502 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 41 | config SPL_SYS_DCACHE_OFF |
| 42 | bool "Do not enable dcache in SPL" |
| 43 | depends on SPL |
| 44 | default SYS_DCACHE_OFF |
| 45 | help |
| 46 | Do not enable data cache in SPL. |
| 47 | |
| Jiaxun Yang | bd64275 | 2024-06-18 14:56:05 +0100 | [diff] [blame] | 48 | config XTENSA_SEMIHOSTING |
| 49 | bool "Support semihosting" |
| 50 | help |
| 51 | Enable Xtensa semihosting debugging support. |
| 52 | |
| 53 | choice |
| 54 | prompt "Semihosting interface" |
| 55 | default XTENSA_SIMCALL_ISS |
| 56 | depends on XTENSA_SEMIHOSTING |
| 57 | help |
| 58 | Choose semihosting interface that will be used for serial port, |
| 59 | block device and networking. |
| 60 | |
| 61 | config XTENSA_SIMCALL_ISS |
| 62 | bool "simcall" |
| 63 | help |
| 64 | Use simcall instruction. simcall is only available on simulators, |
| 65 | it does nothing on hardware. |
| 66 | |
| 67 | config XTENSA_SIMCALL_GDBIO |
| 68 | bool "GDBIO" |
| 69 | help |
| 70 | Use break instruction. It is available on real hardware when GDB |
| 71 | is attached to it via JTAG. |
| 72 | |
| 73 | endchoice |
| 74 | |
| Chris Zankel | 7e270ec | 2016-08-10 18:36:48 +0300 | [diff] [blame] | 75 | source "board/cadence/xtfpga/Kconfig" |
| Jiaxun Yang | 206ad6c | 2024-06-18 14:56:09 +0100 | [diff] [blame] | 76 | source "board/emulation/qemu-xtensa/Kconfig" |
| Chris Zankel | c978b52 | 2016-08-10 18:36:44 +0300 | [diff] [blame] | 77 | |
| 78 | endmenu |