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Alison Wang6b57ff62014-05-06 09:13:01 +08001/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * Register definitions for Freescale QSPI
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef _FSL_QSPI_H_
10#define _FSL_QSPI_H_
11
12struct fsl_qspi_regs {
13 u32 mcr;
14 u32 rsvd0[1];
15 u32 ipcr;
16 u32 flshcr;
17 u32 buf0cr;
18 u32 buf1cr;
19 u32 buf2cr;
20 u32 buf3cr;
21 u32 bfgencr;
22 u32 soccr;
23 u32 rsvd1[2];
24 u32 buf0ind;
25 u32 buf1ind;
26 u32 buf2ind;
27 u32 rsvd2[49];
28 u32 sfar;
29 u32 rsvd3[1];
30 u32 smpr;
31 u32 rbsr;
32 u32 rbct;
33 u32 rsvd4[15];
34 u32 tbsr;
35 u32 tbdr;
36 u32 rsvd5[1];
37 u32 sr;
38 u32 fr;
39 u32 rser;
40 u32 spndst;
41 u32 sptrclr;
42 u32 rsvd6[4];
43 u32 sfa1ad;
44 u32 sfa2ad;
45 u32 sfb1ad;
46 u32 sfb2ad;
47 u32 rsvd7[28];
48 u32 rbdr[32];
49 u32 rsvd8[32];
50 u32 lutkey;
51 u32 lckcr;
52 u32 rsvd9[2];
53 u32 lut[64];
54};
55
56#define QSPI_IPCR_SEQID_SHIFT 24
57#define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT)
58
59#define QSPI_MCR_END_CFD_SHIFT 2
60#define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT)
Peng Fan5f7f70c2015-01-08 10:40:20 +080061#ifdef CONFIG_SYS_FSL_QSPI_AHB
62/* AHB needs 64bit operation */
63#define QSPI_MCR_END_CFD_LE (3 << QSPI_MCR_END_CFD_SHIFT)
64#else
Alison Wang6b57ff62014-05-06 09:13:01 +080065#define QSPI_MCR_END_CFD_LE (1 << QSPI_MCR_END_CFD_SHIFT)
Peng Fan5f7f70c2015-01-08 10:40:20 +080066#endif
Alison Wang6b57ff62014-05-06 09:13:01 +080067#define QSPI_MCR_DDR_EN_SHIFT 7
68#define QSPI_MCR_DDR_EN_MASK (1 << QSPI_MCR_DDR_EN_SHIFT)
69#define QSPI_MCR_CLR_RXF_SHIFT 10
70#define QSPI_MCR_CLR_RXF_MASK (1 << QSPI_MCR_CLR_RXF_SHIFT)
71#define QSPI_MCR_CLR_TXF_SHIFT 11
72#define QSPI_MCR_CLR_TXF_MASK (1 << QSPI_MCR_CLR_TXF_SHIFT)
73#define QSPI_MCR_MDIS_SHIFT 14
74#define QSPI_MCR_MDIS_MASK (1 << QSPI_MCR_MDIS_SHIFT)
75#define QSPI_MCR_RESERVED_SHIFT 16
76#define QSPI_MCR_RESERVED_MASK (0xf << QSPI_MCR_RESERVED_SHIFT)
Peng Fan5f7f70c2015-01-08 10:40:20 +080077#define QSPI_MCR_SWRSTHD_SHIFT 1
78#define QSPI_MCR_SWRSTHD_MASK (1 << QSPI_MCR_SWRSTHD_SHIFT)
79#define QSPI_MCR_SWRSTSD_SHIFT 0
80#define QSPI_MCR_SWRSTSD_MASK (1 << QSPI_MCR_SWRSTSD_SHIFT)
Alison Wang6b57ff62014-05-06 09:13:01 +080081
82#define QSPI_SMPR_HSENA_SHIFT 0
83#define QSPI_SMPR_HSENA_MASK (1 << QSPI_SMPR_HSENA_SHIFT)
84#define QSPI_SMPR_FSPHS_SHIFT 5
85#define QSPI_SMPR_FSPHS_MASK (1 << QSPI_SMPR_FSPHS_SHIFT)
86#define QSPI_SMPR_FSDLY_SHIFT 6
87#define QSPI_SMPR_FSDLY_MASK (1 << QSPI_SMPR_FSDLY_SHIFT)
88#define QSPI_SMPR_DDRSMP_SHIFT 16
89#define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT)
90
Peng Fan5f7f70c2015-01-08 10:40:20 +080091#define QSPI_BUFXCR_INVALID_MSTRID 0xe
92#define QSPI_BUF3CR_ALLMST_SHIFT 31
93#define QSPI_BUF3CR_ALLMST_MASK (1 << QSPI_BUF3CR_ALLMST_SHIFT)
94#define QSPI_BUF3CR_ADATSZ_SHIFT 8
95#define QSPI_BUF3CR_ADATSZ_MASK (0xFF << QSPI_BUF3CR_ADATSZ_SHIFT)
96
Alison Wang6b57ff62014-05-06 09:13:01 +080097#define QSPI_BFGENCR_SEQID_SHIFT 12
98#define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT)
99#define QSPI_BFGENCR_PAR_EN_SHIFT 16
100#define QSPI_BFGENCR_PAR_EN_MASK (1 << QSPI_BFGENCR_PAR_EN_SHIFT)
101
102#define QSPI_RBSR_RDBFL_SHIFT 8
103#define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT)
104
105#define QSPI_RBCT_RXBRD_SHIFT 8
106#define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT)
107
Suresh Gupta1c631da2017-08-30 20:06:33 +0530108#define QSPI_SR_AHB_ACC_SHIFT 2
109#define QSPI_SR_AHB_ACC_MASK (1 << QSPI_SR_AHB_ACC_SHIFT)
110#define QSPI_SR_IP_ACC_SHIFT 1
111#define QSPI_SR_IP_ACC_MASK (1 << QSPI_SR_IP_ACC_SHIFT)
Alison Wang6b57ff62014-05-06 09:13:01 +0800112#define QSPI_SR_BUSY_SHIFT 0
113#define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT)
114
115#define QSPI_LCKCR_LOCK 0x1
116#define QSPI_LCKCR_UNLOCK 0x2
117
118#define LUT_KEY_VALUE 0x5af05af0
119
120#define OPRND0_SHIFT 0
121#define OPRND0(x) ((x) << OPRND0_SHIFT)
122#define PAD0_SHIFT 8
123#define PAD0(x) ((x) << PAD0_SHIFT)
124#define INSTR0_SHIFT 10
125#define INSTR0(x) ((x) << INSTR0_SHIFT)
126#define OPRND1_SHIFT 16
127#define OPRND1(x) ((x) << OPRND1_SHIFT)
128#define PAD1_SHIFT 24
129#define PAD1(x) ((x) << PAD1_SHIFT)
130#define INSTR1_SHIFT 26
131#define INSTR1(x) ((x) << INSTR1_SHIFT)
132
133#define LUT_CMD 1
134#define LUT_ADDR 2
135#define LUT_DUMMY 3
136#define LUT_READ 7
137#define LUT_WRITE 8
138
139#define LUT_PAD1 0
140#define LUT_PAD2 1
141#define LUT_PAD4 2
142
143#define ADDR24BIT 0x18
144#define ADDR32BIT 0x20
145
146#endif /* _FSL_QSPI_H_ */