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Jason Liu938080d2011-05-13 01:58:55 +00001/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Jason Liu938080d2011-05-13 01:58:55 +00006 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/imx-regs.h>
Jason Liu938080d2011-05-13 01:58:55 +000011#include <asm/arch/sys_proto.h>
12#include <asm/arch/crm_regs.h>
Stefano Babicf92e4e62012-02-22 00:24:41 +000013#include <asm/arch/clock.h>
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +000014#include <asm/arch/iomux-mx53.h>
Jason Liu938080d2011-05-13 01:58:55 +000015#include <asm/arch/clock.h>
16#include <asm/errno.h>
Vikram Narayanan30ea4be2012-11-10 02:32:46 +000017#include <asm/imx-common/mx5_video.h>
Jason Liu938080d2011-05-13 01:58:55 +000018#include <netdev.h>
19#include <i2c.h>
20#include <mmc.h>
21#include <fsl_esdhc.h>
Stefano Babic50410072011-08-21 10:59:33 +020022#include <asm/gpio.h>
Łukasz Majewskic7336812012-11-13 03:21:55 +000023#include <power/pmic.h>
Fabio Estevame7e33722012-04-30 08:12:04 +000024#include <dialog_pmic.h>
Fabio Estevam5b547f32012-05-07 10:25:59 +000025#include <fsl_pmic.h>
Fabio Estevamf714b0a2012-05-10 15:07:35 +000026#include <linux/fb.h>
27#include <ipu_pixfmt.h>
28
Fabio Estevam3ef0a312012-08-21 10:01:56 +000029#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
Jason Liu938080d2011-05-13 01:58:55 +000030
31DECLARE_GLOBAL_DATA_PTR;
32
Marek Vasut31c832f2014-03-28 08:30:59 +010033static uint32_t mx53_dram_size[2];
34
35phys_size_t get_effective_memsize(void)
36{
37 /*
38 * WARNING: We must override get_effective_memsize() function here
39 * to report only the size of the first DRAM bank. This is to make
40 * U-Boot relocator place U-Boot into valid memory, that is, at the
41 * end of the first DRAM bank. If we did not override this function
42 * like so, U-Boot would be placed at the address of the first DRAM
43 * bank + total DRAM size - sizeof(uboot), which in the setup where
44 * each DRAM bank contains 512MiB of DRAM would result in placing
45 * U-Boot into invalid memory area close to the end of the first
46 * DRAM bank.
47 */
48 return mx53_dram_size[0];
49}
50
Jason Liu938080d2011-05-13 01:58:55 +000051int dram_init(void)
52{
Marek Vasut31c832f2014-03-28 08:30:59 +010053 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
54 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
Jason Liu938080d2011-05-13 01:58:55 +000055
Marek Vasut31c832f2014-03-28 08:30:59 +010056 gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
Jason Liu938080d2011-05-13 01:58:55 +000057
58 return 0;
59}
Marek Vasut31c832f2014-03-28 08:30:59 +010060
Jason Liu938080d2011-05-13 01:58:55 +000061void dram_init_banksize(void)
62{
63 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
Marek Vasut31c832f2014-03-28 08:30:59 +010064 gd->bd->bi_dram[0].size = mx53_dram_size[0];
Jason Liu938080d2011-05-13 01:58:55 +000065
66 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
Marek Vasut31c832f2014-03-28 08:30:59 +010067 gd->bd->bi_dram[1].size = mx53_dram_size[1];
Jason Liu938080d2011-05-13 01:58:55 +000068}
69
Fabio Estevam54cd1de2012-05-08 03:40:49 +000070u32 get_board_rev(void)
71{
72 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
73 struct fuse_bank *bank = &iim->bank[0];
74 struct fuse_bank0_regs *fuse =
75 (struct fuse_bank0_regs *)bank->fuse_regs;
76
77 int rev = readl(&fuse->gp[6]);
78
Fabio Estevameae08eb2012-05-29 05:54:39 +000079 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
80 rev = 0;
81
Fabio Estevam54cd1de2012-05-08 03:40:49 +000082 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
83}
84
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +000085#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
86 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
87
Jason Liu938080d2011-05-13 01:58:55 +000088static void setup_iomux_uart(void)
89{
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +000090 static const iomux_v3_cfg_t uart_pads[] = {
91 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
92 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
93 };
Jason Liu938080d2011-05-13 01:58:55 +000094
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +000095 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
Jason Liu938080d2011-05-13 01:58:55 +000096}
97
Wolfgang Grandegger45cf6ad2011-11-11 14:03:37 +010098#ifdef CONFIG_USB_EHCI_MX5
Anatolij Gustschin60bae5e2011-12-12 01:25:46 +000099int board_ehci_hcd_init(int port)
Wolfgang Grandegger45cf6ad2011-11-11 14:03:37 +0100100{
Fabio Estevam6ecaee82012-05-07 10:42:57 +0000101 /* request VBUS power enable pin, GPIO7_8 */
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000102 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
103 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
Anatolij Gustschin60bae5e2011-12-12 01:25:46 +0000104 return 0;
Wolfgang Grandegger45cf6ad2011-11-11 14:03:37 +0100105}
106#endif
107
Jason Liu938080d2011-05-13 01:58:55 +0000108static void setup_iomux_fec(void)
109{
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000110 static const iomux_v3_cfg_t fec_pads[] = {
111 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
112 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
113 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
114 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
115 PAD_CTL_HYS | PAD_CTL_PKE),
116 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
117 PAD_CTL_HYS | PAD_CTL_PKE),
118 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
119 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
120 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
121 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
122 PAD_CTL_HYS | PAD_CTL_PKE),
123 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
124 PAD_CTL_HYS | PAD_CTL_PKE),
125 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
126 PAD_CTL_HYS | PAD_CTL_PKE),
127 };
Jason Liu938080d2011-05-13 01:58:55 +0000128
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000129 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
Jason Liu938080d2011-05-13 01:58:55 +0000130}
131
132#ifdef CONFIG_FSL_ESDHC
133struct fsl_esdhc_cfg esdhc_cfg[2] = {
Benoît Thébaudeau16e43f32012-08-13 07:28:16 +0000134 {MMC_SDHC1_BASE_ADDR},
135 {MMC_SDHC3_BASE_ADDR},
Jason Liu938080d2011-05-13 01:58:55 +0000136};
137
Thierry Reding314284b2012-01-02 01:15:36 +0000138int board_mmc_getcd(struct mmc *mmc)
Jason Liu938080d2011-05-13 01:58:55 +0000139{
140 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
Thierry Reding314284b2012-01-02 01:15:36 +0000141 int ret;
Jason Liu938080d2011-05-13 01:58:55 +0000142
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000143 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530144 gpio_direction_input(IMX_GPIO_NR(3, 11));
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000145 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530146 gpio_direction_input(IMX_GPIO_NR(3, 13));
Fabio Estevam73128aa2011-11-15 05:51:29 +0000147
Jason Liu938080d2011-05-13 01:58:55 +0000148 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530149 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
Jason Liu938080d2011-05-13 01:58:55 +0000150 else
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530151 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
Jason Liu938080d2011-05-13 01:58:55 +0000152
Thierry Reding314284b2012-01-02 01:15:36 +0000153 return ret;
Jason Liu938080d2011-05-13 01:58:55 +0000154}
155
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000156#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
157 PAD_CTL_PUS_100K_UP)
158#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
159 PAD_CTL_DSE_HIGH)
160
Jason Liu938080d2011-05-13 01:58:55 +0000161int board_mmc_init(bd_t *bis)
162{
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000163 static const iomux_v3_cfg_t sd1_pads[] = {
164 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
165 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
166 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
167 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
168 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
169 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
170 MX53_PAD_EIM_DA13__GPIO3_13,
171 };
172
173 static const iomux_v3_cfg_t sd2_pads[] = {
174 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
175 SD_CMD_PAD_CTRL),
176 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
177 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
178 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
179 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
180 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
181 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
182 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
183 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
184 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
185 MX53_PAD_EIM_DA11__GPIO3_11,
186 };
187
Jason Liu938080d2011-05-13 01:58:55 +0000188 u32 index;
Fabio Estevam17695022014-11-15 14:50:27 -0200189 int ret;
Jason Liu938080d2011-05-13 01:58:55 +0000190
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000191 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
192 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
193
Jason Liu938080d2011-05-13 01:58:55 +0000194 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
195 switch (index) {
196 case 0:
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000197 imx_iomux_v3_setup_multiple_pads(sd1_pads,
198 ARRAY_SIZE(sd1_pads));
Jason Liu938080d2011-05-13 01:58:55 +0000199 break;
200 case 1:
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000201 imx_iomux_v3_setup_multiple_pads(sd2_pads,
202 ARRAY_SIZE(sd2_pads));
Jason Liu938080d2011-05-13 01:58:55 +0000203 break;
204 default:
205 printf("Warning: you configured more ESDHC controller"
206 "(%d) as supported by the board(2)\n",
207 CONFIG_SYS_FSL_ESDHC_NUM);
Fabio Estevam17695022014-11-15 14:50:27 -0200208 return -EINVAL;
Jason Liu938080d2011-05-13 01:58:55 +0000209 }
Fabio Estevam17695022014-11-15 14:50:27 -0200210 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
211 if (ret)
212 return ret;
Jason Liu938080d2011-05-13 01:58:55 +0000213 }
214
Fabio Estevam17695022014-11-15 14:50:27 -0200215 return 0;
Jason Liu938080d2011-05-13 01:58:55 +0000216}
217#endif
218
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000219#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
220 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
221
Fabio Estevame7e33722012-04-30 08:12:04 +0000222static void setup_iomux_i2c(void)
223{
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000224 static const iomux_v3_cfg_t i2c1_pads[] = {
225 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
226 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
227 };
228
229 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
Fabio Estevame7e33722012-04-30 08:12:04 +0000230}
231
232static int power_init(void)
233{
Fabio Estevam5b547f32012-05-07 10:25:59 +0000234 unsigned int val;
Fabio Estevam085e7282012-12-28 04:05:29 +0000235 int ret;
Fabio Estevame7e33722012-04-30 08:12:04 +0000236 struct pmic *p;
237
Fabio Estevam5b547f32012-05-07 10:25:59 +0000238 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
Fabio Estevamd2292512012-12-28 04:05:28 +0000239 ret = pmic_dialog_init(I2C_PMIC);
240 if (ret)
241 return ret;
Łukasz Majewskic7336812012-11-13 03:21:55 +0000242
243 p = pmic_get("DIALOG_PMIC");
244 if (!p)
245 return -ENODEV;
Fabio Estevame7e33722012-04-30 08:12:04 +0000246
Fabio Estevam4ccaf5d2014-11-10 17:38:19 -0200247 setenv("fdt_file", "imx53-qsb.dtb");
248
Fabio Estevam5b547f32012-05-07 10:25:59 +0000249 /* Set VDDA to 1.25V */
250 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
251 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
Fabio Estevam085e7282012-12-28 04:05:29 +0000252 if (ret) {
253 printf("Writing to BUCKCORE_REG failed: %d\n", ret);
254 return ret;
255 }
Fabio Estevame7e33722012-04-30 08:12:04 +0000256
Fabio Estevam085e7282012-12-28 04:05:29 +0000257 pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
Fabio Estevam5b547f32012-05-07 10:25:59 +0000258 val |= DA9052_SUPPLY_VBCOREGO;
Fabio Estevam085e7282012-12-28 04:05:29 +0000259 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
260 if (ret) {
261 printf("Writing to SUPPLY_REG failed: %d\n", ret);
262 return ret;
263 }
Fabio Estevame7e33722012-04-30 08:12:04 +0000264
Fabio Estevam5b547f32012-05-07 10:25:59 +0000265 /* Set Vcc peripheral to 1.30V */
Fabio Estevam085e7282012-12-28 04:05:29 +0000266 ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
267 if (ret) {
268 printf("Writing to BUCKPRO_REG failed: %d\n", ret);
269 return ret;
270 }
271
272 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
273 if (ret) {
274 printf("Writing to SUPPLY_REG failed: %d\n", ret);
275 return ret;
276 }
277
278 return ret;
Fabio Estevam5b547f32012-05-07 10:25:59 +0000279 }
280
281 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
Fabio Estevam570aa2f2013-11-20 21:17:36 -0200282 ret = pmic_init(I2C_0);
Fabio Estevamd2292512012-12-28 04:05:28 +0000283 if (ret)
284 return ret;
Łukasz Majewskic7336812012-11-13 03:21:55 +0000285
Fabio Estevam89651122012-12-11 06:36:58 +0000286 p = pmic_get("FSL_PMIC");
Łukasz Majewskic7336812012-11-13 03:21:55 +0000287 if (!p)
288 return -ENODEV;
Fabio Estevam5b547f32012-05-07 10:25:59 +0000289
Fabio Estevam4ccaf5d2014-11-10 17:38:19 -0200290 setenv("fdt_file", "imx53-qsrb.dtb");
291
Fabio Estevam5b547f32012-05-07 10:25:59 +0000292 /* Set VDDGP to 1.25V for 1GHz on SW1 */
293 pmic_reg_read(p, REG_SW_0, &val);
294 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
295 ret = pmic_reg_write(p, REG_SW_0, val);
Fabio Estevam085e7282012-12-28 04:05:29 +0000296 if (ret) {
297 printf("Writing to REG_SW_0 failed: %d\n", ret);
298 return ret;
299 }
Fabio Estevam5b547f32012-05-07 10:25:59 +0000300
301 /* Set VCC as 1.30V on SW2 */
302 pmic_reg_read(p, REG_SW_1, &val);
303 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
Fabio Estevam085e7282012-12-28 04:05:29 +0000304 ret = pmic_reg_write(p, REG_SW_1, val);
305 if (ret) {
306 printf("Writing to REG_SW_1 failed: %d\n", ret);
307 return ret;
308 }
Fabio Estevam5b547f32012-05-07 10:25:59 +0000309
310 /* Set global reset timer to 4s */
311 pmic_reg_read(p, REG_POWER_CTL2, &val);
312 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
Fabio Estevam085e7282012-12-28 04:05:29 +0000313 ret = pmic_reg_write(p, REG_POWER_CTL2, val);
314 if (ret) {
315 printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
316 return ret;
317 }
Fabio Estevam768a0592012-05-07 10:26:00 +0000318
319 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
320 pmic_reg_read(p, REG_MODE_0, &val);
321 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
Fabio Estevam085e7282012-12-28 04:05:29 +0000322 ret = pmic_reg_write(p, REG_MODE_0, val);
323 if (ret) {
324 printf("Writing to REG_MODE_0 failed: %d\n", ret);
325 return ret;
326 }
Fabio Estevam768a0592012-05-07 10:26:00 +0000327
328 /* Set SWBST to 5V in auto mode */
329 val = SWBST_AUTO;
Fabio Estevam085e7282012-12-28 04:05:29 +0000330 ret = pmic_reg_write(p, SWBST_CTRL, val);
331 if (ret) {
332 printf("Writing to SWBST_CTRL failed: %d\n", ret);
333 return ret;
334 }
335
336 return ret;
Fabio Estevam5b547f32012-05-07 10:25:59 +0000337 }
Fabio Estevame7e33722012-04-30 08:12:04 +0000338
Fabio Estevam085e7282012-12-28 04:05:29 +0000339 return -1;
Fabio Estevame7e33722012-04-30 08:12:04 +0000340}
341
342static void clock_1GHz(void)
343{
344 int ret;
Benoît Thébaudeau833b6432012-09-27 10:19:58 +0000345 u32 ref_clk = MXC_HCLK;
Fabio Estevame7e33722012-04-30 08:12:04 +0000346 /*
347 * After increasing voltage to 1.25V, we can switch
348 * CPU clock to 1GHz and DDR to 400MHz safely
349 */
350 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
351 if (ret)
352 printf("CPU: Switch CPU clock to 1GHZ failed\n");
353
354 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
355 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
356 if (ret)
357 printf("CPU: Switch DDR clock to 400MHz failed\n");
358}
359
Jason Liu938080d2011-05-13 01:58:55 +0000360int board_early_init_f(void)
361{
362 setup_iomux_uart();
363 setup_iomux_fec();
Vikram Narayanan30ea4be2012-11-10 02:32:46 +0000364 setup_iomux_lcd();
Jason Liu938080d2011-05-13 01:58:55 +0000365
366 return 0;
367}
368
Masahiro Yamada365475e2014-02-13 18:30:26 +0900369#if defined(CONFIG_DISPLAY_CPUINFO)
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000370int print_cpuinfo(void)
371{
372 u32 cpurev;
373
374 cpurev = get_cpu_rev();
375 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
376 (cpurev & 0xFF000) >> 12,
377 (cpurev & 0x000F0) >> 4,
378 (cpurev & 0x0000F) >> 0,
379 mxc_get_clock(MXC_ARM_CLK) / 1000000);
380 printf("Reset cause: %s\n", get_reset_cause());
381 return 0;
382}
Masahiro Yamada365475e2014-02-13 18:30:26 +0900383#endif
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000384
Stefano Babic3e077372012-08-05 00:18:53 +0000385/*
386 * Do not overwrite the console
387 * Use always serial for U-Boot console
388 */
389int overwrite_console(void)
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000390{
Stefano Babic3e077372012-08-05 00:18:53 +0000391 return 1;
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000392}
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000393
Jason Liu938080d2011-05-13 01:58:55 +0000394int board_init(void)
395{
Jason Liu938080d2011-05-13 01:58:55 +0000396 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
397
Stefano Babicf92e4e62012-02-22 00:24:41 +0000398 mxc_set_sata_internal_clock();
Fabio Estevameae08eb2012-05-29 05:54:39 +0000399 setup_iomux_i2c();
Fabio Estevam54bb8412012-12-26 05:50:20 +0000400
Fabio Estevam54bb8412012-12-26 05:50:20 +0000401 return 0;
402}
403
404int board_late_init(void)
405{
Fabio Estevameae08eb2012-05-29 05:54:39 +0000406 if (!power_init())
407 clock_1GHz();
408 print_cpuinfo();
Stefano Babicf92e4e62012-02-22 00:24:41 +0000409
Jason Liu938080d2011-05-13 01:58:55 +0000410 return 0;
411}
412
413int checkboard(void)
414{
415 puts("Board: MX53 LOCO\n");
416
417 return 0;
418}