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York Sunf749db32014-06-23 15:15:56 -07001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <fsl_ddr_sdram.h>
9#include <fsl_ddr_dimm_params.h>
10#include "ddr.h"
11
12DECLARE_GLOBAL_DATA_PTR;
13
14void fsl_ddr_board_options(memctl_options_t *popts,
15 dimm_params_t *pdimm,
16 unsigned int ctrl_num)
17{
18 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
19 ulong ddr_freq;
20
21 if (ctrl_num > 3) {
22 printf("Not supported controller number %d\n", ctrl_num);
23 return;
24 }
25 if (!pdimm->n_ranks)
26 return;
27
28 /*
29 * we use identical timing for all slots. If needed, change the code
30 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
31 */
32 if (popts->registered_dimm_en)
York Sund9c68b12014-08-13 10:21:05 -070033 pbsp = rdimms[ctrl_num];
York Sunf749db32014-06-23 15:15:56 -070034 else
York Sund9c68b12014-08-13 10:21:05 -070035 pbsp = udimms[ctrl_num];
York Sunf749db32014-06-23 15:15:56 -070036
37
38 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
39 * freqency and n_banks specified in board_specific_parameters table.
40 */
41 ddr_freq = get_ddr_freq(0) / 1000000;
42 while (pbsp->datarate_mhz_high) {
43 if (pbsp->n_ranks == pdimm->n_ranks &&
44 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
45 if (ddr_freq <= pbsp->datarate_mhz_high) {
46 popts->clk_adjust = pbsp->clk_adjust;
47 popts->wrlvl_start = pbsp->wrlvl_start;
48 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
49 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
50 goto found;
51 }
52 pbsp_highest = pbsp;
53 }
54 pbsp++;
55 }
56
57 if (pbsp_highest) {
58 printf("Error: board specific timing not found for data rate %lu MT/s\n"
59 "Trying to use the highest speed (%u) parameters\n",
60 ddr_freq, pbsp_highest->datarate_mhz_high);
61 popts->clk_adjust = pbsp_highest->clk_adjust;
62 popts->wrlvl_start = pbsp_highest->wrlvl_start;
63 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
64 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
65 } else {
66 panic("DIMM is not supported by this board");
67 }
68found:
69 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
70 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
71 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
72 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
73 pbsp->wrlvl_ctl_3);
74
York Sund9c68b12014-08-13 10:21:05 -070075 if (ctrl_num == CONFIG_DP_DDR_CTRL) {
76 /* force DDR bus width to 32 bits */
77 popts->data_bus_width = 1;
78 popts->otf_burst_chop_en = 0;
79 popts->burst_length = DDR_BL8;
80 }
York Sunf749db32014-06-23 15:15:56 -070081 /*
82 * Factors to consider for half-strength driver enable:
83 * - number of DIMMs installed
84 */
85 popts->half_strength_driver_enable = 1;
86 /*
87 * Write leveling override
88 */
89 popts->wrlvl_override = 1;
90 popts->wrlvl_sample = 0xf;
91
92 /*
93 * Rtt and Rtt_WR override
94 */
95 popts->rtt_override = 0;
96
97 /* Enable ZQ calibration */
98 popts->zq_en = 1;
99
100#ifdef CONFIG_SYS_FSL_DDR4
101 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
102 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
103 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
104#else
105 /* DHC_EN =1, ODT = 75 Ohm */
106 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
107 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
108#endif
109}
110
111#ifdef CONFIG_SYS_DDR_RAW_TIMING
112dimm_params_t ddr_raw_timing = {
113 .n_ranks = 2,
114 .rank_density = 1073741824u,
115 .capacity = 2147483648,
116 .primary_sdram_width = 64,
117 .ec_sdram_width = 0,
118 .registered_dimm = 0,
119 .mirrored_dimm = 0,
120 .n_row_addr = 14,
121 .n_col_addr = 10,
122 .n_banks_per_sdram_device = 8,
123 .edc_config = 0,
124 .burst_lengths_bitmask = 0x0c,
125
126 .tckmin_x_ps = 937,
127 .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
128 .taa_ps = 13090,
129 .twr_ps = 15000,
130 .trcd_ps = 13090,
131 .trrd_ps = 5000,
132 .trp_ps = 13090,
133 .tras_ps = 33000,
134 .trc_ps = 46090,
135 .trfc_ps = 160000,
136 .twtr_ps = 7500,
137 .trtp_ps = 7500,
138 .refresh_rate_ps = 7800000,
139 .tfaw_ps = 25000,
140};
141
142int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
143 unsigned int controller_number,
144 unsigned int dimm_number)
145{
146 const char dimm_model[] = "Fixed DDR on board";
147
148 if (((controller_number == 0) && (dimm_number == 0)) ||
149 ((controller_number == 1) && (dimm_number == 0))) {
150 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
151 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
152 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
153 }
154
155 return 0;
156}
157#endif
158phys_size_t initdram(int board_type)
159{
160 phys_size_t dram_size;
161
162 puts("Initializing DDR....");
163
164 puts("using SPD\n");
165 dram_size = fsl_ddr_sdram();
166
167 return dram_size;
168}
169
170void dram_init_banksize(void)
171{
York Sund9c68b12014-08-13 10:21:05 -0700172#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
173 phys_size_t dp_ddr_size;
174#endif
175
York Sunf749db32014-06-23 15:15:56 -0700176 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
177 if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
178 gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
179 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
180 gd->bd->bi_dram[1].size = gd->ram_size -
181 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
182 } else {
183 gd->bd->bi_dram[0].size = gd->ram_size;
184 }
York Sund9c68b12014-08-13 10:21:05 -0700185
186#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
187 /* initialize DP-DDR here */
188 puts("DP-DDR: ");
189 /*
190 * DDR controller use 0 as the base address for binding.
191 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
192 */
193 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
194 CONFIG_DP_DDR_CTRL,
195 CONFIG_DP_DDR_NUM_CTRLS,
196 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
197 NULL, NULL, NULL);
198 if (dp_ddr_size) {
199 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
200 gd->bd->bi_dram[2].size = dp_ddr_size;
201 } else {
202 puts("Not detected");
203 }
204#endif
York Sunf749db32014-06-23 15:15:56 -0700205}