blob: 08fc4e84276a73f54e3e4970fd357f918f8de24b [file] [log] [blame]
Poonam Aggrwal49249e12011-02-09 19:17:53 +00001/*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * P010 RDB board configuration file
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30#ifdef CONFIG_36BIT
31#define CONFIG_PHYS_64BIT
32#endif
33
34#ifdef CONFIG_P1010RDB
35#define CONFIG_P1010
Dipen Dudhatd793e5a2011-07-28 14:47:28 -050036#define CONFIG_NAND_FSL_IFC
Poonam Aggrwal49249e12011-02-09 19:17:53 +000037#endif
38
39#ifdef CONFIG_SDCARD
40#define CONFIG_RAMBOOT_SDCARD
41#define CONFIG_SYS_TEXT_BASE 0x11000000
42#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
43#endif
44
45#ifdef CONFIG_SPIFLASH
46#define CONFIG_RAMBOOT_SPIFLASH
47#define CONFIG_SYS_TEXT_BASE 0x11000000
48#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
49#endif
50
Dipen Dudhatd793e5a2011-07-28 14:47:28 -050051#ifdef CONFIG_NAND /* NAND Boot */
52#define CONFIG_RAMBOOT_NAND
53#define CONFIG_NAND_U_BOOT
54#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
55#ifdef CONFIG_NAND_SPL
56#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
57#else
58#define CONFIG_SYS_TEXT_BASE 0x11001000
59#endif /* CONFIG_NAND_SPL */
60#endif
61
Ruchika Gupta2f439e82011-06-08 22:52:48 -050062
63#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
64#define CONFIG_RAMBOOT_NAND
65#define CONFIG_SYS_TEXT_BASE 0x11000000
66#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
67#endif
68
Poonam Aggrwal49249e12011-02-09 19:17:53 +000069#ifndef CONFIG_SYS_TEXT_BASE
70#define CONFIG_SYS_TEXT_BASE 0xeff80000
71#endif
72
73#ifndef CONFIG_RESET_VECTOR_ADDRESS
74#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
75#endif
76
77#ifndef CONFIG_SYS_MONITOR_BASE
78#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
79#endif
80
81/* High Level Configuration Options */
82#define CONFIG_BOOKE /* BOOKE */
83#define CONFIG_E500 /* BOOKE e500 family */
84#define CONFIG_MPC85xx
85#define CONFIG_FSL_IFC /* Enable IFC Support */
86#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
87
88#define CONFIG_PCI /* Enable PCI/PCIE */
89#if defined(CONFIG_PCI)
90#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
91#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
92#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
93#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
94#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
95
96#define CONFIG_CMD_NET
97#define CONFIG_CMD_PCI
98
99#define CONFIG_E1000 /* E1000 pci Ethernet card*/
100
101/*
102 * PCI Windows
103 * Memory space is mapped 1-1, but I/O space must start from 0.
104 */
105/* controller 1, Slot 1, tgtid 1, Base address a000 */
106#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
107#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
108#ifdef CONFIG_PHYS_64BIT
109#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
110#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
111#else
112#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
113#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
114#endif
115#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
116#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
117#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
118#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
119#ifdef CONFIG_PHYS_64BIT
120#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
121#else
122#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
123#endif
124
125/* controller 2, Slot 2, tgtid 2, Base address 9000 */
126#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
127#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
128#ifdef CONFIG_PHYS_64BIT
129#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
130#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
131#else
132#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
133#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
134#endif
135#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
136#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
137#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
138#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
139#ifdef CONFIG_PHYS_64BIT
140#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
141#else
142#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
143#endif
144
145#define CONFIG_PCI_PNP /* do pci plug-and-play */
146
147#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
148#define CONFIG_DOS_PARTITION
149#endif
150
151#define CONFIG_FSL_LAW /* Use common FSL init code */
152#define CONFIG_TSEC_ENET
153#define CONFIG_ENV_OVERWRITE
154
155#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
156#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
157
158#ifndef CONFIG_SDCARD
159#define CONFIG_MISC_INIT_R
160#endif
161
162#define CONFIG_HWCONFIG
163/*
164 * These can be toggled for performance analysis, otherwise use default.
165 */
166#define CONFIG_L2_CACHE /* toggle L2 cache */
167#define CONFIG_BTB /* toggle branch predition */
168
169#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
170
171#define CONFIG_ENABLE_36BIT_PHYS
172
173#ifdef CONFIG_PHYS_64BIT
174#define CONFIG_ADDR_MAP 1
175#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
176#endif
177
178#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
179#define CONFIG_SYS_MEMTEST_END 0x1fffffff
180#define CONFIG_PANIC_HANG /* do not reset board on panic */
181
182/* DDR Setup */
183#define CONFIG_FSL_DDR3
York Sun1ba62f12012-02-29 12:36:51 +0000184#define CONFIG_SYS_DDR_RAW_TIMING
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000185#define CONFIG_DDR_SPD
186#define CONFIG_SYS_SPD_BUS_NUM 1
187#define SPD_EEPROM_ADDRESS 0x52
188
189#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
190
191#ifndef __ASSEMBLY__
192extern unsigned long get_sdram_size(void);
193#endif
194#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
195#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
196#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
197
198#define CONFIG_DIMM_SLOTS_PER_CTLR 1
199#define CONFIG_CHIP_SELECTS_PER_CTRL 1
200
201/* DDR3 Controller Settings */
202#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
203#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
204#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
205#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
206#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
207#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
208#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
209
210#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
211#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
212#define CONFIG_SYS_DDR_RCW_1 0x00000000
213#define CONFIG_SYS_DDR_RCW_2 0x00000000
214#define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */
215#define CONFIG_SYS_DDR_CONTROL_2 0x04401010
216#define CONFIG_SYS_DDR_TIMING_4 0x00000001
217#define CONFIG_SYS_DDR_TIMING_5 0x03402400
218
219#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
220#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
221#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644
222#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
223#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
224#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
225#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
226#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
227#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
228
229/* settings for DDR3 at 667MT/s */
230#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
231#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
232#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
233#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
234#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
235#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
236#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
237#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
238#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
239
240#define CONFIG_SYS_CCSRBAR 0xffe00000
241#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
242
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500243/* Don't relocate CCSRBAR while in NAND_SPL */
244#ifdef CONFIG_NAND_SPL
245#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
246#endif
247
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000248/*
249 * Memory map
250 *
251 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
252 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
253 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
254 *
255 * Localbus non-cacheable
256 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
257 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
258 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
259 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
260 */
261
262/* In case of SD card boot, IFC interface is not available because of muxing */
263#ifdef CONFIG_SDCARD
264#define CONFIG_SYS_NO_FLASH
265#else
266/*
267 * IFC Definitions
268 */
269/* NOR Flash on IFC */
270#define CONFIG_SYS_FLASH_BASE 0xee000000
271#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
272
273#ifdef CONFIG_PHYS_64BIT
274#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
275#else
276#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
277#endif
278
279#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
280 CSPR_PORT_SIZE_16 | \
281 CSPR_MSEL_NOR | \
282 CSPR_V)
283#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
284#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
285/* NOR Flash Timing Params */
286#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
287 FTIM0_NOR_TEADC(0x5) | \
288 FTIM0_NOR_TEAHC(0x5)
289#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
290 FTIM1_NOR_TRAD_NOR(0x0f)
291#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
292 FTIM2_NOR_TCH(0x4) | \
293 FTIM2_NOR_TWP(0x1c)
294#define CONFIG_SYS_NOR_FTIM3 0x0
295
296#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
297#define CONFIG_SYS_FLASH_QUIET_TEST
298#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
299#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
300
301#undef CONFIG_SYS_FLASH_CHECKSUM
302#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
303#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
304
305/* CFI for NOR Flash */
306#define CONFIG_FLASH_CFI_DRIVER
307#define CONFIG_SYS_FLASH_CFI
308#define CONFIG_SYS_FLASH_EMPTY_INFO
309#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
310
311/* NAND Flash on IFC */
312#define CONFIG_SYS_NAND_BASE 0xff800000
313#ifdef CONFIG_PHYS_64BIT
314#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
315#else
316#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
317#endif
318
319#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
320 | CSPR_PORT_SIZE_8 \
321 | CSPR_MSEL_NAND \
322 | CSPR_V)
323#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
324#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
325 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
326 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
327 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
328 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
329 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
330 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
331
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500332#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
333#define CONFIG_SYS_MAX_NAND_DEVICE 1
334#define CONFIG_MTD_NAND_VERIFY_WRITE
335#define CONFIG_CMD_NAND
336#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
337
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000338/* NAND Flash Timing Params */
339#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
340 FTIM0_NAND_TWP(0x0C) | \
341 FTIM0_NAND_TWCHT(0x04) | \
342 FTIM0_NAND_TWH(0x05)
343#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
344 FTIM1_NAND_TWBE(0x1d) | \
345 FTIM1_NAND_TRR(0x07) | \
346 FTIM1_NAND_TRP(0x0c)
347#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
348 FTIM2_NAND_TREH(0x05) | \
349 FTIM2_NAND_TWHRE(0x0f)
350#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
351
352#define CONFIG_SYS_NAND_DDR_LAW 11
353
354/* Set up IFC registers for boot location NOR/NAND */
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500355#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SECBOOT)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500356#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
357#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
358#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
359#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
360#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
361#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
362#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
363#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
364#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
365#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
366#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
367#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
368#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
369#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
370#else
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000371#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
372#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
373#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
374#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
375#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
376#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
377#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
378#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
379#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
380#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
381#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
382#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
383#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
384#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500385#endif
386
387/* NAND boot: 8K NAND loader config */
388#define CONFIG_SYS_NAND_SPL_SIZE 0x2000
389#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
390#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
391#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
392#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
393#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000
394#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000395
396/* CPLD on IFC */
397#define CONFIG_SYS_CPLD_BASE 0xffb00000
398
399#ifdef CONFIG_PHYS_64BIT
400#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
401#else
402#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
403#endif
404
405#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
406 | CSPR_PORT_SIZE_8 \
407 | CSPR_MSEL_GPCM \
408 | CSPR_V)
409#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
410#define CONFIG_SYS_CSOR3 0x0
411/* CPLD Timing parameters for IFC CS3 */
412#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
413 FTIM0_GPCM_TEADC(0x0e) | \
414 FTIM0_GPCM_TEAHC(0x0e))
415#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
416 FTIM1_GPCM_TRAD(0x1f))
417#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
418 FTIM2_GPCM_TCH(0x0) | \
419 FTIM2_GPCM_TWP(0x1f))
420#define CONFIG_SYS_CS3_FTIM3 0x0
421#endif /* CONFIG_SDCARD */
422
423#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
424 defined(CONFIG_RAMBOOT_NAND)
425#define CONFIG_SYS_RAMBOOT
426#define CONFIG_SYS_EXTRA_ENV_RELOC
427#else
428#undef CONFIG_SYS_RAMBOOT
429#endif
430
431#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
432#define CONFIG_BOARD_EARLY_INIT_R
433
434#define CONFIG_SYS_INIT_RAM_LOCK
435#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
436#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
437
438#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
439 - GENERATED_GBL_DATA_SIZE)
440#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
441
442#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
443#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
444
445/* Serial Port */
446#define CONFIG_CONS_INDEX 1
447#undef CONFIG_SERIAL_SOFTWARE_FIFO
448#define CONFIG_SYS_NS16550
449#define CONFIG_SYS_NS16550_SERIAL
450#define CONFIG_SYS_NS16550_REG_SIZE 1
451#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500452#ifdef CONFIG_NAND_SPL
453#define CONFIG_NS16550_MIN_FUNCTIONS
454#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000455
456#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
457#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
458
459#define CONFIG_SYS_BAUDRATE_TABLE \
460 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
461
462#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
463#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
464
465/* Use the HUSH parser */
466#define CONFIG_SYS_HUSH_PARSER
467#ifdef CONFIG_SYS_HUSH_PARSER
468#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
469#endif
470
471/*
472 * Pass open firmware flat tree
473 */
474#define CONFIG_OF_LIBFDT
475#define CONFIG_OF_BOARD_SETUP
476#define CONFIG_OF_STDOUT_VIA_ALIAS
477
478/* new uImage format support */
479#define CONFIG_FIT
480#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
481
482#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
483#define CONFIG_HARD_I2C /* I2C with hardware support */
484#undef CONFIG_SOFT_I2C /* I2C bit-banged */
485#define CONFIG_I2C_MULTI_BUS
486#define CONFIG_I2C_CMD_TREE
487#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
488#define CONFIG_SYS_I2C_SLAVE 0x7F
489#define CONFIG_SYS_I2C_OFFSET 0x3000
490#define CONFIG_SYS_I2C2_OFFSET 0x3100
491
492/* I2C EEPROM */
493#undef CONFIG_ID_EEPROM
494/* enable read and write access to EEPROM */
495#define CONFIG_CMD_EEPROM
496#define CONFIG_SYS_I2C_MULTI_EEPROMS
497#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
498#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
499#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
500
501/* RTC */
502#define CONFIG_RTC_PT7C4338
503#define CONFIG_SYS_I2C_RTC_ADDR 0x68
504
505#define CONFIG_CMD_I2C
506
507/*
508 * SPI interface will not be available in case of NAND boot SPI CS0 will be
509 * used for SLIC
510 */
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500511#if !defined(CONFIG_NAND_U_BOOT) || !defined(CONFIG_NAND_SECBOOT)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000512/* eSPI - Enhanced SPI */
513#define CONFIG_FSL_ESPI
514#define CONFIG_SPI_FLASH
515#define CONFIG_SPI_FLASH_SPANSION
516#define CONFIG_CMD_SF
517#define CONFIG_SF_DEFAULT_SPEED 10000000
518#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500519#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000520
521#if defined(CONFIG_TSEC_ENET)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000522#define CONFIG_MII /* MII PHY management */
523#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
524#define CONFIG_TSEC1 1
525#define CONFIG_TSEC1_NAME "eTSEC1"
526#define CONFIG_TSEC2 1
527#define CONFIG_TSEC2_NAME "eTSEC2"
528#define CONFIG_TSEC3 1
529#define CONFIG_TSEC3_NAME "eTSEC3"
530
531#define TSEC1_PHY_ADDR 1
532#define TSEC2_PHY_ADDR 0
533#define TSEC3_PHY_ADDR 2
534
535#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
536#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
537#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
538
539#define TSEC1_PHYIDX 0
540#define TSEC2_PHYIDX 0
541#define TSEC3_PHYIDX 0
542
543#define CONFIG_ETHPRIME "eTSEC1"
544
545#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
546
547/* TBI PHY configuration for SGMII mode */
548#define CONFIG_TSEC_TBICR_SETTINGS ( \
549 TBICR_PHY_RESET \
550 | TBICR_ANEG_ENABLE \
551 | TBICR_FULL_DUPLEX \
552 | TBICR_SPEED1_SET \
553 )
554
555#endif /* CONFIG_TSEC_ENET */
556
557
558/* SATA */
559#define CONFIG_FSL_SATA
560#define CONFIG_LIBATA
561
562#ifdef CONFIG_FSL_SATA
563#define CONFIG_SYS_SATA_MAX_DEVICE 2
564#define CONFIG_SATA1
565#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
566#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
567#define CONFIG_SATA2
568#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
569#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
570
571#define CONFIG_CMD_SATA
572#define CONFIG_LBA48
573#endif /* #ifdef CONFIG_FSL_SATA */
574
575/* SD interface will only be available in case of SD boot */
576#ifdef CONFIG_SDCARD
577#define CONFIG_MMC
578#define CONFIG_DEF_HWCONFIG esdhc
579#endif
580
581#ifdef CONFIG_MMC
582#define CONFIG_CMD_MMC
583#define CONFIG_DOS_PARTITION
584#define CONFIG_FSL_ESDHC
585#define CONFIG_GENERIC_MMC
586#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
587#endif
588
589#define CONFIG_HAS_FSL_DR_USB
590
591#if defined(CONFIG_HAS_FSL_DR_USB)
592#define CONFIG_USB_EHCI
593
594#ifdef CONFIG_USB_EHCI
595#define CONFIG_CMD_USB
596#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
597#define CONFIG_USB_EHCI_FSL
598#define CONFIG_USB_STORAGE
599#endif
600#endif
601
602/*
603 * Environment
604 */
605#if defined(CONFIG_SYS_RAMBOOT)
606#if defined(CONFIG_RAMBOOT_SDCARD)
607#define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000608#define CONFIG_FSL_FIXED_MMC_LOCATION
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000609#define CONFIG_SYS_MMC_ENV_DEV 0
610#define CONFIG_ENV_SIZE 0x2000
611#elif defined(CONFIG_RAMBOOT_SPIFLASH)
612#define CONFIG_ENV_IS_IN_SPI_FLASH
613#define CONFIG_ENV_SPI_BUS 0
614#define CONFIG_ENV_SPI_CS 0
615#define CONFIG_ENV_SPI_MAX_HZ 10000000
616#define CONFIG_ENV_SPI_MODE 0
617#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
618#define CONFIG_ENV_SECT_SIZE 0x10000
619#define CONFIG_ENV_SIZE 0x2000
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500620#elif defined(CONFIG_NAND_U_BOOT)
621#define CONFIG_ENV_IS_IN_NAND
622#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
623#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE
624#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000625#else
626#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
627#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
628#define CONFIG_ENV_SIZE 0x2000
629#endif
630#else
631#define CONFIG_ENV_IS_IN_FLASH
632#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
633#define CONFIG_ENV_ADDR 0xfff80000
634#else
635#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
636#endif
637#define CONFIG_ENV_SIZE 0x2000
638#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
639#endif
640
641#define CONFIG_LOADS_ECHO /* echo on for serial download */
642#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
643
644/*
645 * Command line configuration.
646 */
647#include <config_cmd_default.h>
648
649#define CONFIG_CMD_DATE
650#define CONFIG_CMD_ERRATA
651#define CONFIG_CMD_ELF
652#define CONFIG_CMD_IRQ
653#define CONFIG_CMD_MII
654#define CONFIG_CMD_PING
655#define CONFIG_CMD_SETEXPR
656#define CONFIG_CMD_REGINFO
657
658#undef CONFIG_WATCHDOG /* watchdog disabled */
659
660#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
661 || defined(CONFIG_FSL_SATA)
662#define CONFIG_CMD_EXT2
663#define CONFIG_CMD_FAT
664#define CONFIG_DOS_PARTITION
665#endif
666
667/*
668 * Miscellaneous configurable options
669 */
670#define CONFIG_SYS_LONGHELP /* undef to save memory */
671#define CONFIG_CMDLINE_EDITING /* Command-line editing */
672#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
673#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
674#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
675
676#if defined(CONFIG_CMD_KGDB)
677#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
678#else
679#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
680#endif
681#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
682 /* Print Buffer Size */
683#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
684#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
685#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
686
687/*
688 * Internal Definitions
689 *
690 * Boot Flags
691 */
692#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
693#define BOOTFLAG_WARM 0x02 /* Software reboot */
694
695/*
696 * For booting Linux, the board info and command line data
697 * have to be in the first 64 MB of memory, since this is
698 * the maximum mapped by the Linux kernel during initialization.
699 */
700#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
701#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
702
703#if defined(CONFIG_CMD_KGDB)
704#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
705#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
706#endif
707
708/*
709 * Environment Configuration
710 */
711
712#if defined(CONFIG_TSEC_ENET)
713#define CONFIG_HAS_ETH0
714#define CONFIG_HAS_ETH1
715#define CONFIG_HAS_ETH2
716#endif
717
718#define CONFIG_HOSTNAME P1010RDB
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000719#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000720#define CONFIG_BOOTFILE "uImage"
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000721#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
722
723/* default location for tftp and bootm */
724#define CONFIG_LOADADDR 1000000
725
726#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
727#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
728
729#define CONFIG_BAUDRATE 115200
730
731#define CONFIG_EXTRA_ENV_SETTINGS \
732 "hwconfig=" MK_STR(CONFIG_DEF_HWCONFIG) "\0" \
733 "netdev=eth0\0" \
734 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
735 "loadaddr=1000000\0" \
736 "consoledev=ttyS0\0" \
737 "ramdiskaddr=2000000\0" \
738 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
739 "fdtaddr=c00000\0" \
740 "fdtfile=p1010rdb.dtb\0" \
741 "bdev=sda1\0" \
742 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
743 "othbootargs=ramdisk_size=600000\0" \
744 "usbfatboot=setenv bootargs root=/dev/ram rw " \
745 "console=$consoledev,$baudrate $othbootargs; " \
746 "usb start;" \
747 "fatload usb 0:2 $loadaddr $bootfile;" \
748 "fatload usb 0:2 $fdtaddr $fdtfile;" \
749 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
750 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
751 "usbext2boot=setenv bootargs root=/dev/ram rw " \
752 "console=$consoledev,$baudrate $othbootargs; " \
753 "usb start;" \
754 "ext2load usb 0:4 $loadaddr $bootfile;" \
755 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
756 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
757 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
758
759#define CONFIG_RAMBOOTCOMMAND \
760 "setenv bootargs root=/dev/ram rw " \
761 "console=$consoledev,$baudrate $othbootargs; " \
762 "tftp $ramdiskaddr $ramdiskfile;" \
763 "tftp $loadaddr $bootfile;" \
764 "tftp $fdtaddr $fdtfile;" \
765 "bootm $loadaddr $ramdiskaddr $fdtaddr"
766
767#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
768
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500769#ifdef CONFIG_SECURE_BOOT
770#include <asm/fsl_secure_boot.h>
771#endif
772
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000773#endif /* __CONFIG_H */