blob: dde49889895a84fe5c6f888e6871952c25374c3d [file] [log] [blame]
Fabio Estevame2d282a2013-03-15 10:43:48 +00001/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
Otavio Salvador8bc7c482014-05-01 19:02:31 -03003 * Copyright (C) 2014 O.S. Systems Software LTDA.
Fabio Estevame2d282a2013-03-15 10:43:48 +00004 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Fabio Estevame2d282a2013-03-15 10:43:48 +00008 */
9
10#include <asm/arch/clock.h>
Fabio Estevam7bcb9832013-05-23 07:50:23 +000011#include <asm/arch/crm_regs.h>
Fabio Estevame2d282a2013-03-15 10:43:48 +000012#include <asm/arch/iomux.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/mx6-pins.h>
Fabio Estevam7bcb9832013-05-23 07:50:23 +000015#include <asm/arch/mxc_hdmi.h>
Fabio Estevame2d282a2013-03-15 10:43:48 +000016#include <asm/arch/sys_proto.h>
17#include <asm/gpio.h>
Stefano Babic552a8482017-06-29 10:16:06 +020018#include <asm/mach-imx/iomux-v3.h>
19#include <asm/mach-imx/mxc_i2c.h>
20#include <asm/mach-imx/boot_mode.h>
21#include <asm/mach-imx/video.h>
22#include <asm/mach-imx/sata.h>
Fabio Estevame2d282a2013-03-15 10:43:48 +000023#include <asm/io.h>
Alexey Brodkin1ace4022014-02-26 17:47:58 +040024#include <linux/sizes.h>
Fabio Estevame2d282a2013-03-15 10:43:48 +000025#include <common.h>
26#include <fsl_esdhc.h>
27#include <mmc.h>
28#include <miiphy.h>
29#include <netdev.h>
Fabio Estevam2fb63962014-02-15 14:52:00 -020030#include <phy.h>
Fabio Estevam67a9abe2014-02-15 14:52:01 -020031#include <input.h>
Otavio Salvador8bc7c482014-05-01 19:02:31 -030032#include <i2c.h>
Fabio Estevame2d282a2013-03-15 10:43:48 +000033
34DECLARE_GLOBAL_DATA_PTR;
35
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000036#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
Fabio Estevame2d282a2013-03-15 10:43:48 +000039
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000040#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
Fabio Estevame2d282a2013-03-15 10:43:48 +000043
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000044#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
Fabio Estevame2d282a2013-03-15 10:43:48 +000046
Otavio Salvador8bc7c482014-05-01 19:02:31 -030047#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
49 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
50
Otavio Salvador5ed15732013-04-19 03:42:02 +000051#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
Otavio Salvador08f32f72013-04-19 03:42:01 +000052#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
Fabio Estevame2d282a2013-03-15 10:43:48 +000053#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
Fabio Estevam9a8804a2015-05-21 19:24:05 -030054#define REV_DETECTION IMX_GPIO_NR(2, 28)
Fabio Estevame2d282a2013-03-15 10:43:48 +000055
56int dram_init(void)
57{
Fabio Estevam0d1ea052015-05-11 20:50:22 -030058 gd->ram_size = imx_ddr_size();
Fabio Estevame2d282a2013-03-15 10:43:48 +000059
60 return 0;
61}
62
63static iomux_v3_cfg_t const uart1_pads[] = {
Fabio Estevam0d1ea052015-05-11 20:50:22 -030064 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
65 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
Fabio Estevame2d282a2013-03-15 10:43:48 +000066};
67
Fabio Estevamafb92662014-02-15 14:51:58 -020068static iomux_v3_cfg_t const usdhc1_pads[] = {
Fabio Estevam0d1ea052015-05-11 20:50:22 -030069 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
70 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
71 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
72 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
73 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
Otavio Salvador5ed15732013-04-19 03:42:02 +000075 /* Carrier MicroSD Card Detect */
Fabio Estevam0d1ea052015-05-11 20:50:22 -030076 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
Otavio Salvador5ed15732013-04-19 03:42:02 +000077};
78
Fabio Estevame2d282a2013-03-15 10:43:48 +000079static iomux_v3_cfg_t const usdhc3_pads[] = {
Fabio Estevam0d1ea052015-05-11 20:50:22 -030080 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
81 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
82 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
83 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
84 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
85 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
Otavio Salvador08f32f72013-04-19 03:42:01 +000086 /* SOM MicroSD Card Detect */
Fabio Estevam0d1ea052015-05-11 20:50:22 -030087 IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
Fabio Estevame2d282a2013-03-15 10:43:48 +000088};
89
90static iomux_v3_cfg_t const enet_pads[] = {
Fabio Estevam0d1ea052015-05-11 20:50:22 -030091 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
92 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
93 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
94 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
95 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
96 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
97 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
98 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
99 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
100 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
101 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
102 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
103 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
104 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
105 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
Fabio Estevame2d282a2013-03-15 10:43:48 +0000106 /* AR8031 PHY Reset */
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300107 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
Fabio Estevame2d282a2013-03-15 10:43:48 +0000108};
109
Fabio Estevam9a8804a2015-05-21 19:24:05 -0300110static iomux_v3_cfg_t const rev_detection_pad[] = {
111 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
112};
113
Fabio Estevame2d282a2013-03-15 10:43:48 +0000114static void setup_iomux_uart(void)
115{
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300116 SETUP_IOMUX_PADS(uart1_pads);
Fabio Estevame2d282a2013-03-15 10:43:48 +0000117}
118
119static void setup_iomux_enet(void)
120{
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300121 SETUP_IOMUX_PADS(enet_pads);
Fabio Estevame2d282a2013-03-15 10:43:48 +0000122
123 /* Reset AR8031 PHY */
124 gpio_direction_output(ETH_PHY_RESET, 0);
Fabio Estevam59a6ca52016-01-05 17:02:54 -0200125 mdelay(10);
Fabio Estevame2d282a2013-03-15 10:43:48 +0000126 gpio_set_value(ETH_PHY_RESET, 1);
Fabio Estevam59a6ca52016-01-05 17:02:54 -0200127 udelay(100);
Fabio Estevame2d282a2013-03-15 10:43:48 +0000128}
129
Otavio Salvador5ed15732013-04-19 03:42:02 +0000130static struct fsl_esdhc_cfg usdhc_cfg[2] = {
Fabio Estevame2d282a2013-03-15 10:43:48 +0000131 {USDHC3_BASE_ADDR},
Otavio Salvador5ed15732013-04-19 03:42:02 +0000132 {USDHC1_BASE_ADDR},
Fabio Estevame2d282a2013-03-15 10:43:48 +0000133};
134
Otavio Salvador08f32f72013-04-19 03:42:01 +0000135int board_mmc_getcd(struct mmc *mmc)
136{
137 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
138 int ret = 0;
139
140 switch (cfg->esdhc_base) {
Otavio Salvador5ed15732013-04-19 03:42:02 +0000141 case USDHC1_BASE_ADDR:
142 ret = !gpio_get_value(USDHC1_CD_GPIO);
143 break;
Otavio Salvador08f32f72013-04-19 03:42:01 +0000144 case USDHC3_BASE_ADDR:
145 ret = !gpio_get_value(USDHC3_CD_GPIO);
146 break;
147 }
148
149 return ret;
150}
151
Fabio Estevame2d282a2013-03-15 10:43:48 +0000152int board_mmc_init(bd_t *bis)
153{
Fabio Estevam05beb8e2014-11-15 14:50:26 -0200154 int ret;
Otavio Salvador5ed15732013-04-19 03:42:02 +0000155 u32 index = 0;
Fabio Estevame2d282a2013-03-15 10:43:48 +0000156
Otavio Salvador5ed15732013-04-19 03:42:02 +0000157 /*
158 * Following map is done:
Bin Menga1875592016-02-05 19:30:11 -0800159 * (U-Boot device node) (Physical Port)
Otavio Salvador5ed15732013-04-19 03:42:02 +0000160 * mmc0 SOM MicroSD
161 * mmc1 Carrier board MicroSD
162 */
163 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
164 switch (index) {
165 case 0:
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300166 SETUP_IOMUX_PADS(usdhc3_pads);
Otavio Salvador5ed15732013-04-19 03:42:02 +0000167 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
168 usdhc_cfg[0].max_bus_width = 4;
169 gpio_direction_input(USDHC3_CD_GPIO);
170 break;
171 case 1:
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300172 SETUP_IOMUX_PADS(usdhc1_pads);
Otavio Salvador5ed15732013-04-19 03:42:02 +0000173 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
174 usdhc_cfg[1].max_bus_width = 4;
175 gpio_direction_input(USDHC1_CD_GPIO);
176 break;
177 default:
178 printf("Warning: you configured more USDHC controllers"
179 "(%d) then supported by the board (%d)\n",
180 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
Fabio Estevam05beb8e2014-11-15 14:50:26 -0200181 return -EINVAL;
Otavio Salvador5ed15732013-04-19 03:42:02 +0000182 }
Abbas Razaaad46592013-03-25 09:13:34 +0000183
Fabio Estevam05beb8e2014-11-15 14:50:26 -0200184 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
185 if (ret)
186 return ret;
Otavio Salvador5ed15732013-04-19 03:42:02 +0000187 }
188
Fabio Estevam05beb8e2014-11-15 14:50:26 -0200189 return 0;
Fabio Estevame2d282a2013-03-15 10:43:48 +0000190}
191
Fabio Estevamdac09fc2016-11-01 14:58:16 -0200192static int ar8031_phy_fixup(struct phy_device *phydev)
193{
194 unsigned short val;
195
196 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
197 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
198 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
199 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
200
201 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
202 val &= 0xffe3;
203 val |= 0x18;
204 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
205
206 /* introduce tx clock delay */
207 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
208 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
209 val |= 0x0100;
210 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
211
212 return 0;
213}
214
215int board_phy_config(struct phy_device *phydev)
216{
217 ar8031_phy_fixup(phydev);
218
219 if (phydev->drv->config)
220 phydev->drv->config(phydev);
221
222 return 0;
223}
224
Fabio Estevam7bcb9832013-05-23 07:50:23 +0000225#if defined(CONFIG_VIDEO_IPUV3)
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300226struct i2c_pads_info mx6q_i2c2_pad_info = {
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300227 .scl = {
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300228 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300229 | MUX_PAD_CTRL(I2C_PAD_CTRL),
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300230 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300231 | MUX_PAD_CTRL(I2C_PAD_CTRL),
232 .gp = IMX_GPIO_NR(4, 12)
233 },
234 .sda = {
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300235 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300236 | MUX_PAD_CTRL(I2C_PAD_CTRL),
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300237 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
238 | MUX_PAD_CTRL(I2C_PAD_CTRL),
239 .gp = IMX_GPIO_NR(4, 13)
240 }
241};
242
243struct i2c_pads_info mx6dl_i2c2_pad_info = {
244 .scl = {
245 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
246 | MUX_PAD_CTRL(I2C_PAD_CTRL),
247 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
248 | MUX_PAD_CTRL(I2C_PAD_CTRL),
249 .gp = IMX_GPIO_NR(4, 12)
250 },
251 .sda = {
252 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
253 | MUX_PAD_CTRL(I2C_PAD_CTRL),
254 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300255 | MUX_PAD_CTRL(I2C_PAD_CTRL),
256 .gp = IMX_GPIO_NR(4, 13)
257 }
Fabio Estevam7bcb9832013-05-23 07:50:23 +0000258};
259
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300260static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300261 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
262 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
263 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
264 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
265 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
266 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
267 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
268 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
269 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
270 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
271 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
272 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
273 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
274 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
275 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
276 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
277 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
278 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
279 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
280 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
281 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
282 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
283 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
284 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
285 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300286};
287
288static void do_enable_hdmi(struct display_info_t const *dev)
Fabio Estevam7bcb9832013-05-23 07:50:23 +0000289{
Pardeep Kumar Singla5ea7f0e2013-07-25 12:12:13 -0500290 imx_enable_hdmi_phy();
Fabio Estevam7bcb9832013-05-23 07:50:23 +0000291}
292
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300293static int detect_i2c(struct display_info_t const *dev)
294{
295 return (0 == i2c_set_bus_num(dev->bus)) &&
296 (0 == i2c_probe(dev->addr));
297}
298
299static void enable_fwadapt_7wvga(struct display_info_t const *dev)
300{
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300301 SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300302
303 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
304 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
305}
306
307struct display_info_t const displays[] = {{
308 .bus = -1,
309 .addr = 0,
310 .pixfmt = IPU_PIX_FMT_RGB24,
311 .detect = detect_hdmi,
312 .enable = do_enable_hdmi,
313 .mode = {
314 .name = "HDMI",
315 .refresh = 60,
316 .xres = 1024,
317 .yres = 768,
318 .pixclock = 15385,
319 .left_margin = 220,
320 .right_margin = 40,
321 .upper_margin = 21,
322 .lower_margin = 7,
323 .hsync_len = 60,
324 .vsync_len = 10,
325 .sync = FB_SYNC_EXT,
326 .vmode = FB_VMODE_NONINTERLACED
327} }, {
328 .bus = 1,
329 .addr = 0x10,
330 .pixfmt = IPU_PIX_FMT_RGB666,
331 .detect = detect_i2c,
332 .enable = enable_fwadapt_7wvga,
333 .mode = {
334 .name = "FWBADAPT-LCD-F07A-0102",
335 .refresh = 60,
336 .xres = 800,
337 .yres = 480,
338 .pixclock = 33260,
339 .left_margin = 128,
340 .right_margin = 128,
341 .upper_margin = 22,
342 .lower_margin = 22,
343 .hsync_len = 1,
344 .vsync_len = 1,
345 .sync = 0,
346 .vmode = FB_VMODE_NONINTERLACED
347} } };
348size_t display_count = ARRAY_SIZE(displays);
349
Fabio Estevam7bcb9832013-05-23 07:50:23 +0000350static void setup_display(void)
351{
352 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
Fabio Estevam7bcb9832013-05-23 07:50:23 +0000353 int reg;
354
Pardeep Kumar Singla5ea7f0e2013-07-25 12:12:13 -0500355 enable_ipu_clock();
356 imx_setup_hdmi();
Fabio Estevam7bcb9832013-05-23 07:50:23 +0000357
358 reg = readl(&mxc_ccm->chsccdr);
Fabio Estevam7bcb9832013-05-23 07:50:23 +0000359 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
Pardeep Kumar Singla5ea7f0e2013-07-25 12:12:13 -0500360 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
Fabio Estevam7bcb9832013-05-23 07:50:23 +0000361 writel(reg, &mxc_ccm->chsccdr);
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300362
363 /* Disable LCD backlight */
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300364 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300365 gpio_direction_input(IMX_GPIO_NR(4, 20));
Fabio Estevam7bcb9832013-05-23 07:50:23 +0000366}
367#endif /* CONFIG_VIDEO_IPUV3 */
368
Fabio Estevame2d282a2013-03-15 10:43:48 +0000369int board_eth_init(bd_t *bis)
370{
Fabio Estevame2d282a2013-03-15 10:43:48 +0000371 setup_iomux_enet();
372
Fabio Estevam14da7592014-01-04 17:36:28 -0200373 return cpu_eth_init(bis);
Fabio Estevame2d282a2013-03-15 10:43:48 +0000374}
375
376int board_early_init_f(void)
377{
378 setup_iomux_uart();
Simon Glass10e40d52017-06-14 21:28:25 -0600379#ifdef CONFIG_SATA
Gilles Chanteperdrixe355eec2016-06-09 10:33:27 +0200380 /* Only mx6q wandboard has SATA */
381 if (is_cpu_type(MXC_CPU_MX6Q))
382 setup_sata();
383#endif
384
Fabio Estevame2d282a2013-03-15 10:43:48 +0000385 return 0;
386}
387
Fabio Estevam7bcb9832013-05-23 07:50:23 +0000388/*
389 * Do not overwrite the console
390 * Use always serial for U-Boot console
391 */
392int overwrite_console(void)
393{
394 return 1;
395}
396
Otavio Salvadoreaffaa22013-04-19 03:42:03 +0000397#ifdef CONFIG_CMD_BMODE
398static const struct boot_mode board_boot_modes[] = {
399 /* 4 bit bus width */
400 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
401 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
402 {NULL, 0},
403};
404#endif
405
Fabio Estevam9a8804a2015-05-21 19:24:05 -0300406static bool is_revc1(void)
407{
408 SETUP_IOMUX_PADS(rev_detection_pad);
409 gpio_direction_input(REV_DETECTION);
410
411 if (gpio_get_value(REV_DETECTION))
412 return true;
413 else
414 return false;
415}
416
Otavio Salvadoreaffaa22013-04-19 03:42:03 +0000417int board_late_init(void)
418{
419#ifdef CONFIG_CMD_BMODE
420 add_board_boot_modes(board_boot_modes);
421#endif
422
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300423#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Breno Lima98b040c2016-07-22 09:11:02 -0300424 if (is_mx6dq())
Simon Glass382bee52017-08-03 12:22:09 -0600425 env_set("board_rev", "MX6Q");
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300426 else
Simon Glass382bee52017-08-03 12:22:09 -0600427 env_set("board_rev", "MX6DL");
Fabio Estevam9a8804a2015-05-21 19:24:05 -0300428
429 if (is_revc1())
Simon Glass382bee52017-08-03 12:22:09 -0600430 env_set("board_name", "C1");
Fabio Estevam9a8804a2015-05-21 19:24:05 -0300431 else
Simon Glass382bee52017-08-03 12:22:09 -0600432 env_set("board_name", "B1");
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300433#endif
Otavio Salvadoreaffaa22013-04-19 03:42:03 +0000434 return 0;
435}
436
Fabio Estevame2d282a2013-03-15 10:43:48 +0000437int board_init(void)
438{
439 /* address of boot parameters */
440 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
441
Sven Ebenfeld36c06272016-11-25 21:42:53 +0100442#if defined(CONFIG_VIDEO_IPUV3)
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300443 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
Breno Lima98b040c2016-07-22 09:11:02 -0300444 if (is_mx6dq())
Fabio Estevam0d1ea052015-05-11 20:50:22 -0300445 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
446 else
447 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
Fabio Estevam1b853e42017-09-22 23:45:30 -0300448
449 setup_display();
Sven Ebenfeld36c06272016-11-25 21:42:53 +0100450#endif
Otavio Salvador8bc7c482014-05-01 19:02:31 -0300451
Fabio Estevame2d282a2013-03-15 10:43:48 +0000452 return 0;
453}
454
Fabio Estevame2d282a2013-03-15 10:43:48 +0000455int checkboard(void)
456{
Fabio Estevam9a8804a2015-05-21 19:24:05 -0300457 if (is_revc1())
458 puts("Board: Wandboard rev C1\n");
459 else
460 puts("Board: Wandboard rev B1\n");
Fabio Estevame2d282a2013-03-15 10:43:48 +0000461
462 return 0;
463}