wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * EMK Elektronik GmbH <www.emk-elektronik.de> |
| 4 | * Reinhard Meyer <r.meyer@emk-elektronik.de> |
| 5 | * |
| 6 | * Board specific routines for the TOP860 |
| 7 | * |
| 8 | * - initialisation |
| 9 | * - interface to VPD data (mac address, clock speeds) |
| 10 | * - memory controller |
| 11 | * - serial io initialisation |
| 12 | * - ethernet io initialisation |
| 13 | * |
| 14 | * ----------------------------------------------------------------- |
Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 15 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <common.h> |
| 19 | #include <commproc.h> |
| 20 | #include <mpc8xx.h> |
Wolfgang Denk | f008b17 | 2011-11-29 22:17:57 +0000 | [diff] [blame] | 21 | #include <asm/io.h> |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 22 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 23 | /***************************************************************************** |
| 24 | * UPM table for 60ns EDO RAM at 25 MHz bus/external clock |
| 25 | *****************************************************************************/ |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 26 | static const uint edo_60ns_25MHz_tbl[] = { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 27 | |
| 28 | /* single read (offset 0x00 in upm ram) */ |
| 29 | 0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00, |
| 30 | 0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05, |
| 31 | /* burst read (offset 0x08 in upm ram) */ |
| 32 | 0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40, |
| 33 | 0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48, |
| 34 | 0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05, |
| 35 | 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, |
| 36 | /* single write (offset 0x18 in upm ram) */ |
| 37 | 0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07, |
| 38 | 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, |
| 39 | /* burst write (offset 0x20 in upm ram) */ |
| 40 | 0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c, |
| 41 | 0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c, |
| 42 | 0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05, |
| 43 | 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, |
| 44 | /* refresh (offset 0x30 in upm ram) */ |
| 45 | 0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04, |
| 46 | 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, |
| 47 | 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, |
| 48 | /* exception (offset 0x3C in upm ram) */ |
| 49 | 0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05, |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 50 | }; |
| 51 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 52 | /***************************************************************************** |
| 53 | * Print Board Identity |
| 54 | *****************************************************************************/ |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 55 | int checkboard (void) |
| 56 | { |
| 57 | puts ("Board:"CONFIG_IDENT_STRING"\n"); |
| 58 | return (0); |
| 59 | } |
| 60 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 61 | /***************************************************************************** |
| 62 | * Initialize DRAM controller |
| 63 | *****************************************************************************/ |
Becky Bruce | 9973e3c | 2008-06-09 16:03:40 -0500 | [diff] [blame] | 64 | phys_size_t initdram (int board_type) |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 65 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 66 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 67 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
| 68 | |
| 69 | /* |
| 70 | * Only initialize memory controller when running from FLASH. |
| 71 | * When running from RAM, don't touch it. |
| 72 | */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 73 | if ((ulong) initdram & 0xff000000) { |
| 74 | volatile uint *addr1, *addr2; |
Wolfgang Denk | f008b17 | 2011-11-29 22:17:57 +0000 | [diff] [blame] | 75 | uint i; |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 76 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 77 | upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl, |
| 78 | sizeof (edo_60ns_25MHz_tbl) / sizeof (uint)); |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 79 | memctl->memc_mptpr = 0x0200; |
| 80 | memctl->memc_mamr = 0x0ca20330; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 81 | memctl->memc_or2 = -CONFIG_SYS_DRAM_MAX | OR_CSNT_SAM; |
| 82 | memctl->memc_br2 = CONFIG_SYS_DRAM_BASE | BR_MS_UPMA | BR_V; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 83 | /* |
| 84 | * Do 8 read accesses to DRAM |
| 85 | */ |
| 86 | addr1 = (volatile uint *) 0; |
| 87 | addr2 = (volatile uint *) 0x00400000; |
Wolfgang Denk | f008b17 | 2011-11-29 22:17:57 +0000 | [diff] [blame] | 88 | for (i = 0; i < 8; i++) |
| 89 | in_be32(addr1); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 90 | |
| 91 | /* |
| 92 | * Now check whether we got 4MB or 16MB populated |
| 93 | */ |
| 94 | addr1[0] = 0x12345678; |
| 95 | addr1[1] = 0x9abcdef0; |
| 96 | addr2[0] = 0xfeedc0de; |
| 97 | addr2[1] = 0x47110815; |
| 98 | if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) { |
| 99 | /* only 4MB populated */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 100 | memctl->memc_or2 = -(CONFIG_SYS_DRAM_MAX / 4) | OR_CSNT_SAM; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 101 | } |
| 102 | } |
| 103 | |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 104 | return -(memctl->memc_or2 & 0xffff0000); |
| 105 | } |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 106 | |
| 107 | /***************************************************************************** |
wdenk | 63e73c9 | 2004-02-23 22:22:28 +0000 | [diff] [blame] | 108 | * prepare for FLASH detection |
| 109 | *****************************************************************************/ |
| 110 | void flash_preinit(void) |
| 111 | { |
| 112 | } |
| 113 | |
| 114 | /***************************************************************************** |
| 115 | * finalize FLASH setup |
| 116 | *****************************************************************************/ |
| 117 | void flash_afterinit(uint bank, ulong start, ulong size) |
| 118 | { |
| 119 | } |
| 120 | |
| 121 | /***************************************************************************** |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 122 | * otherinits after RAM is there and we are relocated to RAM |
| 123 | * note: though this is an int function, nobody cares for the result! |
| 124 | *****************************************************************************/ |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 125 | int misc_init_r (void) |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 126 | { |
| 127 | /* read 'factory' part of EEPROM */ |
wdenk | 63e73c9 | 2004-02-23 22:22:28 +0000 | [diff] [blame] | 128 | extern void read_factory_r (void); |
| 129 | read_factory_r (); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 130 | |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 131 | return (0); |
| 132 | } |