blob: 43cf6bc441c0421fa5dc5d24d837d5705d9e8a68 [file] [log] [blame]
Heiko Schocherf7264c32011-11-29 02:33:47 +00001/*
2 * (C) Copyright 2011
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * Based on:
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * Based on davinci_dvevm.h. Original Copyrights follow:
9 *
10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
11 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocherf7264c32011-11-29 02:33:47 +000013 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * Board
20 */
21#define CONFIG_DRIVER_TI_EMAC
22#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
23#define CONFIG_USE_NAND
24
25/*
26 * SoC Configuration
27 */
28#define CONFIG_ARM926EJS /* arm926ejs CPU core */
29#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
30#define CONFIG_SOC_DA850 /* TI DA850 SoC */
Christian Rieschb67d8812012-02-02 00:44:39 +000031#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Heiko Schocherf7264c32011-11-29 02:33:47 +000032#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
33#define CONFIG_SYS_OSCIN_FREQ 24000000
34#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
35#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
36#define CONFIG_SYS_HZ 1000
Heiko Schocherf7264c32011-11-29 02:33:47 +000037#define CONFIG_DA850_LOWLEVEL
38#define CONFIG_ARCH_CPU_INIT
Sughosh Ganu6b873dc2012-02-02 00:44:41 +000039#define CONFIG_SYS_DA850_PLL_INIT
40#define CONFIG_SYS_DA850_DDR_INIT
Heiko Schocherf7264c32011-11-29 02:33:47 +000041#define CONFIG_DA8XX_GPIO
42#define CONFIG_HOSTNAME enbw_cmc
Heiko Schocherf7264c32011-11-29 02:33:47 +000043
44#define MACH_TYPE_ENBW_CMC 3585
45#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
46
47/*
48 * Memory Info
49 */
50#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
51#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
52#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
53#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
54
55/* memtest start addr */
56#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
57
58/* memtest will be run on 16MB */
59#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
60
61#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Heiko Schocherf7264c32011-11-29 02:33:47 +000062
63/*
64 * Serial Driver info
65 */
66#define CONFIG_SYS_NS16550
67#define CONFIG_SYS_NS16550_SERIAL
68#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
69#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
70#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
71#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
72#define CONFIG_BAUDRATE 115200 /* Default baud rate */
Sughosh Ganu6b873dc2012-02-02 00:44:41 +000073
Heiko Schocherf7264c32011-11-29 02:33:47 +000074/*
75 * I2C Configuration
76 */
77#define CONFIG_HARD_I2C
78#define CONFIG_DRIVER_DAVINCI_I2C
79#define CONFIG_SYS_I2C_SPEED 80000
80#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
81#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
82#define CONFIG_CMD_I2C
83
84#define CONFIG_CMD_DTT
85#define CONFIG_DTT_LM75
86#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
87#define CONFIG_SYS_DTT_MAX_TEMP 70
88#define CONFIG_SYS_DTT_LOW_TEMP -30
89#define CONFIG_SYS_DTT_HYSTERESIS 3
90
91/*
Heiko Schocher14b9f162012-05-14 20:24:14 +000092 * SPI Configuration
93 */
94#define CONFIG_DAVINCI_SPI
95#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
96#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
97#define CONFIG_CMD_SPI
98
99/*
Heiko Schocherf7264c32011-11-29 02:33:47 +0000100 * Flash & Environment
101 */
102#ifdef CONFIG_USE_NAND
103#define CONFIG_NAND_DAVINCI
104#define CONFIG_SYS_NAND_USE_FLASH_BBT
105#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
106#define CONFIG_SYS_NAND_PAGE_2K
107#define CONFIG_SYS_NAND_CS 3
108#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
Eric Benard34fa0702013-04-22 05:55:00 +0000109#define CONFIG_SYS_NAND_MASK_CLE 0x10
110#define CONFIG_SYS_NAND_MASK_ALE 0x8
Heiko Schocherf7264c32011-11-29 02:33:47 +0000111#undef CONFIG_SYS_NAND_HW_ECC
112#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Heiko Schocherf7264c32011-11-29 02:33:47 +0000113
114#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
115#define MTDPARTS_DEFAULT \
116 "mtdparts=" \
117 "physmap-flash.0:" \
118 "512k(U-Boot)," \
119 "64k(env1)," \
120 "64k(env2)," \
121 "-(rest);" \
122 "davinci_nand.1:" \
123 "128k(dtb)," \
124 "3m(kernel)," \
125 "4m(rootfs)," \
126 "-(userfs)"
127
128
129#define CONFIG_CMD_MTDPARTS
130
131#endif
132
133/*
134 * Network & Ethernet Configuration
135 */
136#ifdef CONFIG_DRIVER_TI_EMAC
137#define CONFIG_MII
138#define CONFIG_BOOTP_DEFAULT
139#define CONFIG_BOOTP_DNS
140#define CONFIG_BOOTP_DNS2
141#define CONFIG_BOOTP_SEND_HOSTNAME
142#define CONFIG_NET_RETRY_COUNT 10
Heiko Schocherf7264c32011-11-29 02:33:47 +0000143#endif
144
145/*
146 * Flash configuration
147 */
148#define CONFIG_SYS_FLASH_CFI
149#define CONFIG_FLASH_CFI_DRIVER
150#define CONFIG_FLASH_CFI_MTD
151#define CONFIG_SYS_FLASH_BASE 0x60000000
152#define CONFIG_SYS_FLASH_SIZE 0x01000000
153#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
154#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
155#define CONFIG_SYS_MAX_FLASH_SECT 128
156#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
157
158#define CONFIG_CMD_FLASH
159
160#define CONFIG_ENV_IS_IN_FLASH
161#define CONFIG_SYS_MONITOR_LEN 0x80000
162#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
163 CONFIG_SYS_MONITOR_LEN)
164#define CONFIG_ENV_SECT_SIZE (64 << 10)
165#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
166#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
167 CONFIG_ENV_SECT_SIZE)
168#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
169#undef CONFIG_ENV_IS_IN_NAND
170#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
171 CONFIG_ENV_SECT_SIZE)
172
Heiko Schocherf7264c32011-11-29 02:33:47 +0000173#define CONFIG_EXTRA_ENV_SETTINGS \
174 "u-boot_addr_r=c0000000\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200175 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000176 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200177 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
178 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
179 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000180 " ${filesize};" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200181 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
Heiko Schocherf7264c32011-11-29 02:33:47 +0000182 "netdev=eth0\0" \
183 "rootpath=/opt/eldk-arm/arm\0" \
184 "nfsargs=setenv bootargs root=/dev/nfs rw " \
185 "nfsroot=${serverip}:${rootpath}\0" \
186 "ramargs=setenv bootargs root=/dev/ram rw\0" \
187 "addip=setenv bootargs ${bootargs} " \
188 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
189 ":${hostname}:${netdev}:off panic=1\0" \
190 "kernel_addr_r=c0700000\0" \
191 "fdt_addr_r=c0600000\0" \
192 "ramdisk_addr_r=c0b00000\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200193 "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
194 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
195 "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000196 "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \
197 "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \
198 "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \
199 "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
200 "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
201 "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
202 "addcon=setenv bootargs ${bootargs} console=ttyS2," \
203 "${baudrate}n8\0" \
204 "net_nfs=run load_fdt load_kernel; " \
205 "run nfsargs addip addcon addmtd addmisc;" \
206 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
207 "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
208 "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
209 "bootcmd=run net_nfs\0" \
210 "machid=e01\0" \
211 "key_cmd_0=echo key: 0\0" \
212 "key_cmd_1=echo key: 1\0" \
213 "key_cmd_2=echo key: 2\0" \
214 "key_cmd_3=echo key: 3\0" \
215 "key_magic_0=0\0" \
216 "key_magic_1=1\0" \
217 "key_magic_2=2\0" \
218 "key_magic_3=3\0" \
219 "magic_keys=0123\0" \
Heiko Schocher14b9f162012-05-14 20:24:14 +0000220 "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000221 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
Heiko Schocher14b9f162012-05-14 20:24:14 +0000222 "addmisc=setenv bootargs ${bootargs}\0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000223 "mtdids=" MTDIDS_DEFAULT "\0" \
224 "mtdparts=" MTDPARTS_DEFAULT "\0" \
225 "logversion=2\0" \
226 "\0"
227
228/*
229 * U-Boot general configuration
230 */
231#define CONFIG_BOOTFILE "uImage" /* Boot file name */
232#define CONFIG_SYS_PROMPT "=> " /* Command Prompt */
233#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
234#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
235#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
236#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
237#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
238#define CONFIG_VERSION_VARIABLE
239#define CONFIG_AUTO_COMPLETE
240#define CONFIG_SYS_HUSH_PARSER
Heiko Schocherf7264c32011-11-29 02:33:47 +0000241#define CONFIG_CMDLINE_EDITING
242#define CONFIG_SYS_LONGHELP
243#define CONFIG_CRC32_VERIFY
244#define CONFIG_MX_CYCLIC
245#define CONFIG_BOOTDELAY 3
246#define CONFIG_HWCONFIG
247#define CONFIG_SHOW_BOOT_PROGRESS
248#define CONFIG_BOARD_LATE_INIT
249
250/*
251 * U-Boot commands
252 */
253#include <config_cmd_default.h>
254#define CONFIG_CMD_ENV
255#define CONFIG_CMD_ASKENV
256#define CONFIG_CMD_DHCP
257#define CONFIG_CMD_DIAG
258#define CONFIG_CMD_MII
259#define CONFIG_CMD_PING
260#define CONFIG_CMD_SAVES
261#define CONFIG_CMD_MEMORY
262#define CONFIG_CMD_CACHE
263
Hadli, Manjunath8f5d4682012-02-06 00:30:44 +0000264#ifdef CONFIG_CMD_BDI
265#define CONFIG_CLOCKS
266#endif
267
Heiko Schocherf7264c32011-11-29 02:33:47 +0000268#ifndef CONFIG_DRIVER_TI_EMAC
269#undef CONFIG_CMD_NET
270#undef CONFIG_CMD_DHCP
271#undef CONFIG_CMD_MII
272#undef CONFIG_CMD_PING
273#endif
274
275#ifdef CONFIG_USE_NAND
276#undef CONFIG_CMD_IMLS
277#define CONFIG_CMD_NAND
278
279#define CONFIG_CMD_MTDPARTS
280#define CONFIG_MTD_DEVICE
281#define CONFIG_MTD_PARTITIONS
282#define CONFIG_LZO
283#define CONFIG_RBTREE
284#define CONFIG_CMD_UBI
285#define CONFIG_CMD_UBIFS
286#endif
287
288#if !defined(CONFIG_USE_NAND) && \
289 !defined(CONFIG_USE_NOR) && \
290 !defined(CONFIG_USE_SPIFLASH)
291#define CONFIG_ENV_IS_NOWHERE
292#define CONFIG_SYS_NO_FLASH
293#define CONFIG_ENV_SIZE (16 << 10)
294#undef CONFIG_CMD_IMLS
295#undef CONFIG_CMD_ENV
296#endif
297
298#define CONFIG_SYS_TEXT_BASE 0x60000000
299#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
300#define CONFIG_SYS_SDRAM_BASE 0xc0000000
301#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
302
303#define CONFIG_VERSION_VARIABLE
304#define CONFIG_ENV_OVERWRITE
305
306#define CONFIG_PREBOOT "echo;" \
307 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
308 "echo"
309#define CONFIG_MISC_INIT_R
310
311#define CONFIG_CMC_RESET_PIN 0x04000000
312#define CONFIG_CMC_RESET_TIMEOUT 3
313
314#define CONFIG_HW_WATCHDOG
315#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
316#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
317#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
318
319#define CONFIG_CMD_DATE
320#define CONFIG_RTC_DAVINCI
321
322/* SD/MMC */
323#define CONFIG_MMC
324#define CONFIG_GENERIC_MMC
325#define CONFIG_DAVINCI_MMC
326#define CONFIG_MMC_MBLOCK
327#define CONFIG_DOS_PARTITION
328#define CONFIG_CMD_FAT
329#define CONFIG_CMD_MMC
330
Heiko Schocher14b9f162012-05-14 20:24:14 +0000331/* GPIO */
332#define CONFIG_ENBW_CMC_BOARD_TYPE 57
333#define CONFIG_ENBW_CMC_HW_ID_BIT0 39
334#define CONFIG_ENBW_CMC_HW_ID_BIT1 38
335#define CONFIG_ENBW_CMC_HW_ID_BIT2 35
Heiko Schocherf7264c32011-11-29 02:33:47 +0000336
337/* FDT support */
338#define CONFIG_OF_LIBFDT
339
340/* LowLevel Init */
341/* PLL */
342#define CONFIG_SYS_DV_CLKMODE 0
343#define CONFIG_SYS_DA850_PLL0_POSTDIV 0
344#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
345#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
346#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */
347#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
348#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
349#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
350#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
351
352#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
353#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
354#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
355#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
356
357#define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */
358#define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
359
360/* DDR RAM */
361#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
362 DV_DDR_PHY_EXT_STRBEN | \
363 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
364
365#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
366 (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
367 (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
368 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
369 (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
370 (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
371 (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
372 (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
373 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
374 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
375 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
376
377#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
378
379/*
380 * freq = 150MHz -> t = 7ns
381 */
382#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
383 (0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \
384 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
385 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
386 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
387 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
388 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
389 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
390 (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
391 ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
392
393/*
394 * freq = 150MHz -> t=7ns
395 */
396#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
397 (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
398 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
399 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
400 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
401 (15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
402 (27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
403 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
404 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
405
406#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407
407#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
408#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
409 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
410 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
411 DAVINCI_SYSCFG_SUSPSRC_EMAC |\
412 DAVINCI_SYSCFG_SUSPSRC_I2C)
413
414#define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \
415 DAVINCI_ABCR_WSTROBE(6) | \
416 DAVINCI_ABCR_WHOLD(1) | \
417 DAVINCI_ABCR_RSETUP(2) | \
418 DAVINCI_ABCR_RSTROBE(6) | \
419 DAVINCI_ABCR_RHOLD(1) | \
420 DAVINCI_ABCR_ASIZE_16BIT)
421
422#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
423 DAVINCI_ABCR_WSTROBE(2) | \
424 DAVINCI_ABCR_WHOLD(1) | \
425 DAVINCI_ABCR_RSETUP(1) | \
426 DAVINCI_ABCR_RSTROBE(6) | \
427 DAVINCI_ABCR_RHOLD(1) | \
428 DAVINCI_ABCR_ASIZE_8BIT)
429
430/*
431 * NOR Bootconfiguration word:
432 * Method: Direc boot
433 * EMIFA access mode: 16 Bit
434 */
435#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
436
437#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
Heiko Schocher14b9f162012-05-14 20:24:14 +0000438#define CONFIG_POST_EXTERNAL_WORD_FUNCS
439#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
Heiko Schocherf7264c32011-11-29 02:33:47 +0000440#define CONFIG_LOGBUFFER
441#define CONFIG_SYS_CONSOLE_IS_IN_ENV
442
443#define CONFIG_BOOTCOUNT_LIMIT
444#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
Stefan Roese0044c422012-08-16 17:55:41 +0000445#define CONFIG_SYS_BOOTCOUNT_BE
Heiko Schocherf7264c32011-11-29 02:33:47 +0000446
447#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
448#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
449#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
450#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
451#endif /* __CONFIG_H */