blob: b7bc920f00f82c03561a6dccfa7e752bb368d895 [file] [log] [blame]
Andre Schwarz5e0de0e2008-07-09 18:30:44 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2008
6 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Andre Schwarz5e0de0e2008-07-09 18:30:44 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#include <version.h>
15
16#define CONFIG_MPC5xxx 1
17#define CONFIG_MPC5200 1
18
Wolfgang Denk2ae18242010-10-06 09:05:45 +020019#ifndef CONFIG_SYS_TEXT_BASE
20#define CONFIG_SYS_TEXT_BASE 0xFF800000
21#endif
22
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020024
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020025#define CONFIG_MISC_INIT_R 1
26
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denk17e900b2008-08-12 14:54:04 +020028#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#define CONFIG_SYS_CACHELINE_SHIFT 5
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020030#endif
31
32#define CONFIG_PSC_CONSOLE 1
33#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020035
36#define CONFIG_PCI 1
37#define CONFIG_PCI_PNP 1
38#undef CONFIG_PCI_SCAN_SHOW
39#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
40
41#define CONFIG_PCI_MEM_BUS 0x40000000
42#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
43#define CONFIG_PCI_MEM_SIZE 0x10000000
44
45#define CONFIG_PCI_IO_BUS 0x50000000
46#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
47#define CONFIG_PCI_IO_SIZE 0x01000000
48
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_XLB_PIPELINING 1
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020050#define CONFIG_HIGH_BATS 1
51
52#define MV_CI mvBlueCOUGAR-P
53#define MV_VCI mvBlueCOUGAR-P
54#define MV_FPGA_DATA 0xff860000
André Schwarz28887d82009-08-27 14:48:35 +020055#define MV_FPGA_SIZE 0
André Schwarze3b39f82009-07-17 14:50:24 +020056#define MV_KERNEL_ADDR 0xffd00000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020057#define MV_INITRD_ADDR 0xff900000
André Schwarze3b39f82009-07-17 14:50:24 +020058#define MV_INITRD_LENGTH 0x00400000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020059#define MV_SCRATCH_ADDR 0x00000000
60#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
Peter Tyser3202d332009-09-16 21:38:10 -050061#define MV_SCRIPT_ADDR 0xff840000
62#define MV_SCRIPT_ADDR2 0xff850000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020063#define MV_DTB_ADDR 0xfffc0000
64
65#define CONFIG_SHOW_BOOT_PROGRESS 1
66
67#define MV_KERNEL_ADDR_RAM 0x00100000
68#define MV_DTB_ADDR_RAM 0x00600000
69#define MV_INITRD_ADDR_RAM 0x01000000
70
71/* pass open firmware flat tree */
72#define CONFIG_OF_LIBFDT 1
73#define CONFIG_OF_BOARD_SETUP 1
74
75#define OF_CPU "PowerPC,5200@0"
76#define OF_SOC "soc5200@f0000000"
77#define OF_TBCLK (bd->bi_busfreq / 4)
78#define MV_DTB_NAME mvbc-p.dtb
79#define CONFIG_OF_STDOUT_VIA_ALIAS 1
80
81/*
82 * Supported commands
83 */
84#include <config_cmd_default.h>
85
86#define CONFIG_CMD_CACHE
87#define CONFIG_CMD_NET
88#define CONFIG_CMD_PING
89#define CONFIG_CMD_DHCP
90#define CONFIG_CMD_SDRAM
91#define CONFIG_CMD_PCI
92#define CONFIG_CMD_FPGA
André Schwarze3b39f82009-07-17 14:50:24 +020093#define CONFIG_CMD_I2C
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020094
95#undef CONFIG_WATCHDOG
96
97#define CONFIG_BOOTP_VENDOREX
98#define CONFIG_BOOTP_SUBNETMASK
99#define CONFIG_BOOTP_GATEWAY
100#define CONFIG_BOOTP_DNS
101#define CONFIG_BOOTP_DNS2
102#define CONFIG_BOOTP_HOSTNAME
103#define CONFIG_BOOTP_BOOTFILESIZE
104#define CONFIG_BOOTP_BOOTPATH
105#define CONFIG_BOOTP_NTPSERVER
106#define CONFIG_BOOTP_RANDOM_DELAY
107#define CONFIG_BOOTP_SEND_HOSTNAME
108
109/*
110 * Autoboot
111 */
112#define CONFIG_BOOTDELAY 2
113#define CONFIG_AUTOBOOT_KEYED
114#define CONFIG_AUTOBOOT_STOP_STR "s"
115#define CONFIG_ZERO_BOOTDELAY_CHECK
116#define CONFIG_RESET_TO_RETRY 1000
117
Peter Tyser3202d332009-09-16 21:38:10 -0500118#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
119 then source ${script_addr}; \
120 else source ${script_addr2}; \
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200121 fi;"
122
123#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
124#define CONFIG_ENV_OVERWRITE
125
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200126#define CONFIG_EXTRA_ENV_SETTINGS \
127 "console_nr=0\0" \
128 "console=yes\0" \
129 "stdin=serial\0" \
130 "stdout=serial\0" \
131 "stderr=serial\0" \
132 "fpga=0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200133 "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
134 "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
135 "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
136 "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
137 "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
138 "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
139 "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
140 "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
141 "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
142 "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
143 "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
144 "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
145 "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
146 "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200147 "mv_version=" U_BOOT_VERSION "\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200148 "dhcp_client_id=" __stringify(MV_CI) "\0" \
149 "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200150 "netretry=no\0" \
151 "use_static_ipaddr=no\0" \
152 "static_ipaddr=192.168.90.10\0" \
153 "static_netmask=255.255.255.0\0" \
154 "static_gateway=0.0.0.0\0" \
155 "initrd_name=uInitrd.mvbc-p-rfs\0" \
156 "zcip=no\0" \
157 "netboot=yes\0" \
158 "mvtest=Ff\0" \
159 "tried_bootfromflash=no\0" \
160 "tried_bootfromnet=no\0" \
161 "use_dhcp=yes\0" \
162 "gev_start=yes\0" \
163 "mvbcdma_debug=0\0" \
164 "mvbcia_debug=0\0" \
165 "propdev_debug=0\0" \
166 "gevss_debug=0\0" \
167 "watchdog=1\0" \
André Schwarze3b39f82009-07-17 14:50:24 +0200168 "sensor_cnt=1\0" \
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200169 ""
170
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200171/*
172 * IPB Bus clocking configuration.
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
175#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200176
177/*
178 * Flash configuration
179 */
180#undef CONFIG_FLASH_16BIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200182#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
184#define CONFIG_SYS_FLASH_EMPTY_INFO
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
187#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MAX_FLASH_BANKS 1
190#define CONFIG_SYS_MAX_FLASH_SECT 256
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_LOWBOOT
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200193#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_SIZE 0x00800000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200195
196/*
197 * Environment settings
198 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200199#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#undef CONFIG_SYS_FLASH_PROTECTION
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200201
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200202#define CONFIG_ENV_ADDR 0xFFFE0000
203#define CONFIG_ENV_SIZE 0x10000
204#define CONFIG_ENV_SECT_SIZE 0x10000
205#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
206#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200207
208/*
209 * Memory map
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MBAR 0xF0000000
212#define CONFIG_SYS_SDRAM_BASE 0x00000000
213#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200216#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200217
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200218#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200220
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200221#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
223#define CONFIG_SYS_RAMBOOT 1
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200224#endif
225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
227#define CONFIG_SYS_MONITOR_LEN (512 << 10)
228#define CONFIG_SYS_MALLOC_LEN (512 << 10)
229#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200230
231/*
André Schwarze3b39f82009-07-17 14:50:24 +0200232 * I2C configuration
233 */
234#define CONFIG_HARD_I2C 1
235#define CONFIG_SYS_I2C_MODULE 1
236#define CONFIG_SYS_I2C_SPEED 86000
237#define CONFIG_SYS_I2C_SLAVE 0x7F
238
239/*
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200240 * Ethernet configuration
241 */
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200242#define CONFIG_NET_RETRY_COUNT 5
243
244#define CONFIG_E1000
Wolfgang Denkc4ec6db2008-07-31 13:57:20 +0200245#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200246#undef CONFIG_MPC5xxx_FEC
247#undef CONFIG_PHY_ADDR
248#define CONFIG_NETDEV eth0
249
250/*
251 * Miscellaneous configurable options
252 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_HUSH_PARSER
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200254#define CONFIG_CMDLINE_EDITING
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#undef CONFIG_SYS_LONGHELP
256#define CONFIG_SYS_PROMPT "=> "
Wolfgang Denk17e900b2008-08-12 14:54:04 +0200257#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_CBSIZE 1024
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200259#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_CBSIZE 256
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200261#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
263#define CONFIG_SYS_MAXARGS 16
264#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_MEMTEST_START 0x00800000
267#define CONFIG_SYS_MEMTEST_END 0x02f00000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_HZ 1000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200270
271/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_LOAD_ADDR 0x02000000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200273/* default location for tftp and bootm */
274#define CONFIG_LOADADDR 0x00200000
275
276/*
277 * Various low-level settings
278 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
282#define CONFIG_SYS_HID0_FINAL HID0_ICE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
285#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
286#define CONFIG_SYS_BOOTCS_CFG 0x00047800
287#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
288#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_CS_BURST 0x000000f0
291#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200292
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_RESET_ADDRESS 0x00000100
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200294
295#undef FPGA_DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
Michal Simekb03b25c2013-05-01 18:05:56 +0200297#define CONFIG_FPGA
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200298#define CONFIG_FPGA_ALTERA 1
299#define CONFIG_FPGA_CYCLON2 1
300#define CONFIG_FPGA_COUNT 1
301
302#endif