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Timur Tabic59e1b42010-06-14 15:28:24 -05001/*
2 * Copyright 2010 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Timur Tabic59e1b42010-06-14 15:28:24 -05007 */
8
9#include <common.h>
10#include <asm/mmu.h>
11
12struct fsl_e_tlb_entry tlb_table[] = {
13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 0, 0, BOOKE_PAGESZ_4K, 0),
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
22 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 MAS3_SX|MAS3_SW|MAS3_SR, 0,
24 0, 0, BOOKE_PAGESZ_4K, 0),
25 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
26 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
27 MAS3_SX|MAS3_SW|MAS3_SR, 0,
28 0, 0, BOOKE_PAGESZ_4K, 0),
29
30 /* TLB 1 */
31 /* *I*** - Covers boot page */
32 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
33 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
34 0, 0, BOOKE_PAGESZ_4K, 1),
35
36 /* *I*G* - CCSRBAR */
37 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
38 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
39 0, 1, BOOKE_PAGESZ_1M, 1),
40
Matthew McClintockf45210d2013-02-18 10:02:19 +000041#ifndef CONFIG_SPL_BUILD
Timur Tabic59e1b42010-06-14 15:28:24 -050042 /* W**G* - Flash/promjet, localbus */
43 /* This will be changed to *I*G* after relocation to RAM. */
44 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
45 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
46 0, 2, BOOKE_PAGESZ_256M, 1),
47
48 /* *I*G* - PCI */
49 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
51 0, 3, BOOKE_PAGESZ_1G, 1),
52
53 /* *I*G* - PCI */
54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
55 CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
57 0, 4, BOOKE_PAGESZ_256M, 1),
58
59 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
60 CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
61 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
62 0, 5, BOOKE_PAGESZ_256M, 1),
63
64 /* *I*G* - PCI I/O */
65 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
67 0, 6, BOOKE_PAGESZ_256K, 1),
Matthew McClintockf45210d2013-02-18 10:02:19 +000068#endif
Timur Tabic59e1b42010-06-14 15:28:24 -050069
70 SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
71 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
72 0, 7, BOOKE_PAGESZ_4K, 1),
Matthew McClintockaf253602012-05-18 06:04:17 +000073
Matthew McClintockf45210d2013-02-18 10:02:19 +000074#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
75 /* **** - eSDHC/eSPI/NAND boot */
Matthew McClintockaf253602012-05-18 06:04:17 +000076 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
77 MAS3_SX|MAS3_SW|MAS3_SR, 0,
78 0, 8, BOOKE_PAGESZ_1G, 1),
Matthew McClintockf45210d2013-02-18 10:02:19 +000079 /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
Matthew McClintockaf253602012-05-18 06:04:17 +000080 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
81 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
Matthew McClintockf45210d2013-02-18 10:02:19 +000082 MAS3_SX|MAS3_SW|MAS3_SR, 0,
Matthew McClintockaf253602012-05-18 06:04:17 +000083 0, 9, BOOKE_PAGESZ_1G, 1),
84#endif
Matthew McClintockf45210d2013-02-18 10:02:19 +000085
86#ifdef CONFIG_SYS_NAND_BASE
87 /* *I*G - NAND */
88 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
89 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
90 0, 10, BOOKE_PAGESZ_16K, 1),
91#endif
92
Timur Tabic59e1b42010-06-14 15:28:24 -050093};
94
95int num_tlb_entries = ARRAY_SIZE(tlb_table);