Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 1 | /* |
Matthias Fuchs | bd84ee4 | 2007-07-09 10:10:06 +0200 | [diff] [blame] | 2 | * (C) Copyright 2005-2007 |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/processor.h> |
Matthias Fuchs | bd84ee4 | 2007-07-09 10:10:06 +0200 | [diff] [blame] | 10 | #include <asm/io.h> |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 11 | #include <command.h> |
| 12 | #include <malloc.h> |
| 13 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 14 | DECLARE_GLOBAL_DATA_PTR; |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 15 | |
| 16 | extern void lxt971_no_sleep(void); |
| 17 | |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 18 | int board_early_init_f (void) |
| 19 | { |
| 20 | /* |
| 21 | * IRQ 0-15 405GP internally generated; active high; level sensitive |
| 22 | * IRQ 16 405GP internally generated; active low; level sensitive |
| 23 | * IRQ 17-24 RESERVED |
| 24 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
| 25 | * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive |
| 26 | * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive |
| 27 | * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive |
| 28 | * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive |
| 29 | * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive |
| 30 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive |
| 31 | */ |
Stefan Roese | 952e776 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 32 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
| 33 | mtdcr(UIC0ER, 0x00000000); /* disable all ints */ |
| 34 | mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ |
| 35 | mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ |
| 36 | mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ |
| 37 | mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
| 38 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 39 | |
| 40 | /* |
| 41 | * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us |
| 42 | */ |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 43 | mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 44 | |
| 45 | /* |
| 46 | * Reset CPLD via GPIO12 (CS3) pin |
| 47 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 48 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 49 | udelay(1000); /* wait 1ms */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 50 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 51 | udelay(1000); /* wait 1ms */ |
| 52 | |
| 53 | return 0; |
| 54 | } |
| 55 | |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 56 | int misc_init_r (void) |
| 57 | { |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 58 | /* adjust flash start and offset */ |
| 59 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
| 60 | gd->bd->bi_flashoffset = 0; |
| 61 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 62 | /* |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 63 | * Setup and enable EEPROM write protection |
| 64 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 65 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 66 | |
| 67 | return (0); |
| 68 | } |
| 69 | |
| 70 | |
| 71 | /* |
| 72 | * Check Board Identity: |
| 73 | */ |
Matthias Fuchs | 049216f | 2009-02-20 10:19:18 +0100 | [diff] [blame] | 74 | #define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000) |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 75 | int checkboard (void) |
| 76 | { |
Stefan Roese | 18c5e64 | 2006-01-18 20:06:44 +0100 | [diff] [blame] | 77 | char str[64]; |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 78 | int flashcnt; |
| 79 | int delay; |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 80 | |
| 81 | puts ("Board: "); |
| 82 | |
Wolfgang Denk | cdb7497 | 2010-07-24 21:55:43 +0200 | [diff] [blame] | 83 | if (getenv_f("serial#", str, sizeof(str)) == -1) { |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 84 | puts ("### No HW ID - assuming CMS700"); |
| 85 | } else { |
| 86 | puts(str); |
| 87 | } |
| 88 | |
Matthias Fuchs | 049216f | 2009-02-20 10:19:18 +0100 | [diff] [blame] | 89 | printf(" (PLD-Version=%02d)\n", |
| 90 | in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001))); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 91 | |
| 92 | /* |
| 93 | * Flash LEDs |
| 94 | */ |
| 95 | for (flashcnt = 0; flashcnt < 3; flashcnt++) { |
Matthias Fuchs | 049216f | 2009-02-20 10:19:18 +0100 | [diff] [blame] | 96 | out_8((void *)LED_REG, 0x00); /* LEDs off */ |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 97 | for (delay = 0; delay < 100; delay++) |
| 98 | udelay(1000); |
Matthias Fuchs | 049216f | 2009-02-20 10:19:18 +0100 | [diff] [blame] | 99 | out_8((void *)LED_REG, 0x0f); /* LEDs on */ |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 100 | for (delay = 0; delay < 50; delay++) |
| 101 | udelay(1000); |
| 102 | } |
Matthias Fuchs | 049216f | 2009-02-20 10:19:18 +0100 | [diff] [blame] | 103 | out_8((void *)LED_REG, 0x70); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | /* ------------------------------------------------------------------------- */ |
| 109 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #if defined(CONFIG_SYS_EEPROM_WREN) |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 111 | /* Input: <dev_addr> I2C address of EEPROM device to enable. |
| 112 | * <state> -1: deliver current state |
| 113 | * 0: disable write |
| 114 | * 1: enable write |
| 115 | * Returns: -1: wrong device address |
| 116 | * 0: dis-/en- able done |
| 117 | * 0/1: current state if <state> was -1. |
| 118 | */ |
| 119 | int eeprom_write_enable (unsigned dev_addr, int state) |
| 120 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 121 | if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 122 | return -1; |
| 123 | } else { |
| 124 | switch (state) { |
| 125 | case 1: |
| 126 | /* Enable write access, clear bit GPIO_SINT2. */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 127 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 128 | state = 0; |
| 129 | break; |
| 130 | case 0: |
| 131 | /* Disable write access, set bit GPIO_SINT2. */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 132 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 133 | state = 0; |
| 134 | break; |
| 135 | default: |
| 136 | /* Read current status back. */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 137 | state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 138 | break; |
| 139 | } |
| 140 | } |
| 141 | return state; |
| 142 | } |
| 143 | |
Wolfgang Denk | 54841ab | 2010-06-28 22:00:46 +0200 | [diff] [blame] | 144 | int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 145 | { |
| 146 | int query = argc == 1; |
| 147 | int state = 0; |
| 148 | |
| 149 | if (query) { |
| 150 | /* Query write access state. */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 151 | state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 152 | if (state < 0) { |
| 153 | puts ("Query of write access state failed.\n"); |
| 154 | } else { |
| 155 | printf ("Write access for device 0x%0x is %sabled.\n", |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 157 | state = 0; |
| 158 | } |
| 159 | } else { |
| 160 | if ('0' == argv[1][0]) { |
| 161 | /* Disable write access. */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 162 | state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 163 | } else { |
| 164 | /* Enable write access. */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 165 | state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 166 | } |
| 167 | if (state < 0) { |
| 168 | puts ("Setup of write access state failed.\n"); |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | return state; |
| 173 | } |
| 174 | |
| 175 | U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, |
Wolfgang Denk | a89c33d | 2009-05-24 17:06:54 +0200 | [diff] [blame] | 176 | "Enable / disable / query EEPROM write access", |
| 177 | "" |
| 178 | ); |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 179 | #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 180 | |
| 181 | /* ------------------------------------------------------------------------- */ |
| 182 | |
Stefan Roese | feaedfc | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 183 | void reset_phy(void) |
| 184 | { |
| 185 | #ifdef CONFIG_LXT971_NO_SLEEP |
| 186 | |
| 187 | /* |
| 188 | * Disable sleep mode in LXT971 |
| 189 | */ |
| 190 | lxt971_no_sleep(); |
| 191 | #endif |
| 192 | } |