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Stefan Roese566806c2007-10-05 17:11:30 +02001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese566806c2007-10-05 17:11:30 +02006 */
7
8#include <common.h>
Stefan Roeseb36df562010-09-09 19:18:00 +02009#include <asm/ppc4xx.h>
10#include <asm/ppc405.h>
Stefan Roese566806c2007-10-05 17:11:30 +020011#include <libfdt.h>
Stefan Roese8697e6a2007-12-13 14:52:53 +010012#include <fdt_support.h>
Stefan Roese566806c2007-10-05 17:11:30 +020013#include <asm/processor.h>
Stefan Roese353f2682007-10-23 10:10:08 +020014#include <asm/io.h>
Stefan Roese06dfaee2009-10-02 14:35:16 +020015#include <asm/errno.h>
Stefan Roese566806c2007-10-05 17:11:30 +020016
17#if defined(CONFIG_PCI)
18#include <pci.h>
19#include <asm/4xx_pcie.h>
20#endif
21
22DECLARE_GLOBAL_DATA_PTR;
23
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
Stefan Roese566806c2007-10-05 17:11:30 +020025
Stefan Roese9998b132010-01-21 11:37:31 +010026static int board_cpld_version(void)
27{
28 u32 cpld;
29
30 cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
31 if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
32 /*
33 * Magic not found -> "old" CPLD revision which needs
34 * the "old" EBC configuration
35 */
36 mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
37 EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
38 EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
39 EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
40 EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
41 EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
42 EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
43
44 /*
45 * Return 0 for "old" CPLD version
46 */
47 return 0;
48 }
49
50 /*
51 * Magic found -> "new" CPLD revision which needs no new
52 * EBC configuration
53 */
54 return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
55}
56
Stefan Roese566806c2007-10-05 17:11:30 +020057/*
58 * Board early initialization function
59 */
60int board_early_init_f (void)
61{
62 u32 val;
63
64 /*--------------------------------------------------------------------+
65 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
66 +--------------------------------------------------------------------+
67 +---------------------------------------------------------------------+
68 |Interrupt| Source | Pol. | Sensi.| Crit. |
69 +---------+-----------------------------------+-------+-------+-------+
70 | IRQ 00 | UART0 | High | Level | Non |
71 | IRQ 01 | UART1 | High | Level | Non |
72 | IRQ 02 | IIC0 | High | Level | Non |
73 | IRQ 03 | TBD | High | Level | Non |
74 | IRQ 04 | TBD | High | Level | Non |
75 | IRQ 05 | EBM | High | Level | Non |
76 | IRQ 06 | BGI | High | Level | Non |
77 | IRQ 07 | IIC1 | Rising| Edge | Non |
78 | IRQ 08 | SPI | High | Lvl/ed| Non |
79 | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
80 | IRQ 10 | MAL TX EOB | High | Level | Non |
81 | IRQ 11 | MAL RX EOB | High | Level | Non |
82 | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
83 | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
84 | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
85 | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
86 | IRQ 16 | PCIE0 AL | high | Level | Non |
87 | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
88 | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
89 | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
90 | IRQ 20 | PCIE0 TCR | High | Level | Non |
91 | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
92 | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
93 | IRQ 23 | Security EIP-94 | High | Level | Non |
94 | IRQ 24 | EMAC0 interrupt | High | Level | Non |
95 | IRQ 25 | EMAC1 interrupt | High | Level | Non |
96 | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
97 | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
98 | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
99 | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
100 | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
101 | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
102 |----------------------------------------------------------------------
103 | IRQ 32 | MAL Serr | High | Level | Non |
104 | IRQ 33 | MAL Txde | High | Level | Non |
105 | IRQ 34 | MAL Rxde | High | Level | Non |
106 | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
107 | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
108 | IRQ 37 | EBC | High |Lvl Edg| Non |
109 | IRQ 38 | NDFC | High | Level | Non |
110 | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
111 | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
112 | IRQ 41 | PCIE1 AL | high | Level | Non |
113 | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
114 | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
115 | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
116 | IRQ 45 | PCIE1 TCR | High | Level | Non |
117 | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
118 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
119 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
120 | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
121 | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
122 | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
123 | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
124 | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
125 | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
126 | IRQ 55 | Serial ROM | High | Level | Non |
127 | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
128 | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
129 | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
130 | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
131 | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
132 | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
133 | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
134 |----------------------------------------------------------------------
135 | IRQ 64 | PE0 AL | High | Level | Non |
136 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
137 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
138 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
139 | IRQ 68 | PE0 TCR | High | Level | Non |
140 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
141 | IRQ 70 | PE0 DCR Error | High | Level | Non |
142 | IRQ 71 | Reserved | N/A | N/A | Non |
143 | IRQ 72 | PE1 AL | High | Level | Non |
144 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
145 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
146 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
147 | IRQ 76 | PE1 TCR | High | Level | Non |
148 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
149 | IRQ 78 | PE1 DCR Error | High | Level | Non |
150 | IRQ 79 | Reserved | N/A | N/A | Non |
151 | IRQ 80 | PE2 AL | High | Level | Non |
152 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
153 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
154 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
155 | IRQ 84 | PE2 TCR | High | Level | Non |
156 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
157 | IRQ 86 | PE2 DCR Error | High | Level | Non |
158 | IRQ 87 | Reserved | N/A | N/A | Non |
159 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
160 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
161 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
162 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
163 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
164 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
165 | IRQ 94 | Reserved | N/A | N/A | Non |
166 | IRQ 95 | Reserved | N/A | N/A | Non |
167 |---------------------------------------------------------------------
168 +---------+-----------------------------------+-------+-------+------*/
169 /*--------------------------------------------------------------------+
170 | Initialise UIC registers. Clear all interrupts. Disable all
171 | interrupts.
172 | Set critical interrupt values. Set interrupt polarities. Set
173 | interrupt trigger levels. Make bit 0 High priority. Clear all
174 | interrupts again.
175 +-------------------------------------------------------------------*/
176
Stefan Roese952e7762009-09-24 09:55:50 +0200177 mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
178 mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
179 mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
180 mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
181 mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
182 mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
183 mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
184 mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
Stefan Roese566806c2007-10-05 17:11:30 +0200185
Stefan Roese952e7762009-09-24 09:55:50 +0200186 mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
187 mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
188 mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
189 mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
190 mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
191 mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
192 mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
193 mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
Stefan Roese566806c2007-10-05 17:11:30 +0200194
Stefan Roese952e7762009-09-24 09:55:50 +0200195 mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
196 mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
Stefan Roese566806c2007-10-05 17:11:30 +0200197 /* Except cascade UIC0 and UIC1 */
Stefan Roese952e7762009-09-24 09:55:50 +0200198 mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
199 mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
200 mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
201 mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
202 mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
203 mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
Stefan Roese566806c2007-10-05 17:11:30 +0200204
205 /*
206 * Note: Some cores are still in reset when the chip starts, so
207 * take them out of reset
208 */
209 mtsdr(SDR0_SRST, 0);
210
Stefan Roese566806c2007-10-05 17:11:30 +0200211 /* Configure 405EX for NAND usage */
212 val = SDR0_CUST0_MUX_NDFC_SEL |
213 SDR0_CUST0_NDFC_ENABLE |
214 SDR0_CUST0_NDFC_BW_8_BIT |
215 SDR0_CUST0_NRB_BUSY |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
Stefan Roese566806c2007-10-05 17:11:30 +0200217 mtsdr(SDR0_CUST0, val);
218
Stefan Roese7cfc12a2007-12-08 14:47:34 +0100219 /*
220 * Configure PFC (Pin Function Control) registers
221 * -> Enable USB
222 */
223 val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
224 mtsdr(SDR0_PFC1, val);
225
Stefan Roesea0dd99d2008-01-14 10:05:05 +0100226 /*
Stefan Roese9998b132010-01-21 11:37:31 +0100227 * The CPLD version detection has to be the first access to
228 * the CPLD, so we need to make this access this early and
229 * save the CPLD version for later.
230 */
231 gd->board_type = board_cpld_version();
232
233 /*
Stefan Roesea0dd99d2008-01-14 10:05:05 +0100234 * Configure FPGA register with PCIe reset
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236 out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
Stefan Roesea0dd99d2008-01-14 10:05:05 +0100237 mdelay(50);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238 out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
Stefan Roesea0dd99d2008-01-14 10:05:05 +0100239
Stefan Roese566806c2007-10-05 17:11:30 +0200240 return 0;
241}
242
243int misc_init_r(void)
244{
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200245#ifdef CONFIG_ENV_IS_IN_FLASH
Stefan Roese566806c2007-10-05 17:11:30 +0200246 /* Monitor protection ON by default */
247 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248 -CONFIG_SYS_MONITOR_LEN,
Stefan Roese566806c2007-10-05 17:11:30 +0200249 0xffffffff,
250 &flash_info[0]);
251#endif
252
253 return 0;
254}
255
Stefan Roese70fab192008-05-13 20:22:01 +0200256static int is_405exr(void)
Stefan Roese353f2682007-10-23 10:10:08 +0200257{
258 u32 pvr = get_pvr();
259
Stefan Roese70fab192008-05-13 20:22:01 +0200260 if (pvr & 0x00000004)
261 return 0; /* bit 2 set -> 405EX */
262
263 return 1; /* bit 2 cleared -> 405EXr */
264}
265
266int board_emac_count(void)
267{
Stefan Roese353f2682007-10-23 10:10:08 +0200268 /*
269 * 405EXr only has one EMAC interface, 405EX has two
270 */
Stefan Roese70fab192008-05-13 20:22:01 +0200271 if (is_405exr())
Stefan Roese353f2682007-10-23 10:10:08 +0200272 return 1;
273 else
274 return 2;
275}
276
Stefan Roeseb0b86742009-10-29 15:04:35 +0100277/*
278 * Override the weak default implementation and return the
279 * last PCIe slot number (max number - 1).
280 */
281int board_pcie_last(void)
Stefan Roese353f2682007-10-23 10:10:08 +0200282{
Stefan Roese353f2682007-10-23 10:10:08 +0200283 /*
284 * 405EXr only has one EMAC interface, 405EX has two
285 */
Stefan Roese70fab192008-05-13 20:22:01 +0200286 if (is_405exr())
Stefan Roeseb0b86742009-10-29 15:04:35 +0100287 return 1 - 1;
Stefan Roese353f2682007-10-23 10:10:08 +0200288 else
Stefan Roeseb0b86742009-10-29 15:04:35 +0100289 return 2 - 1;
Stefan Roese353f2682007-10-23 10:10:08 +0200290}
291
Stefan Roese566806c2007-10-05 17:11:30 +0200292int checkboard (void)
293{
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000294 char buf[64];
295 int i = getenv_f("serial#", buf, sizeof(buf));
Stefan Roese566806c2007-10-05 17:11:30 +0200296
Stefan Roese70fab192008-05-13 20:22:01 +0200297 if (is_405exr())
Stefan Roese353f2682007-10-23 10:10:08 +0200298 printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
299 else
300 printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
Stefan Roese566806c2007-10-05 17:11:30 +0200301
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000302 if (i > 0) {
Stefan Roese566806c2007-10-05 17:11:30 +0200303 puts(", serial# ");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000304 puts(buf);
Stefan Roese566806c2007-10-05 17:11:30 +0200305 }
Stefan Roese9998b132010-01-21 11:37:31 +0100306 printf(" (CPLD rev. %ld)\n", gd->board_type);
Stefan Roese566806c2007-10-05 17:11:30 +0200307
308 return (0);
309}