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wdenk2262cfe2002-11-18 00:14:45 +00001/*
2 * (C) Copyright 2002
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02003 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
wdenk2262cfe2002-11-18 00:14:45 +00004 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk2262cfe2002-11-18 00:14:45 +00006 */
7
8/* i8259.h i8259 PIC Registers */
9
10#ifndef _ASMI386_I8259_H_
11#define _ASMI386_I8959_H_ 1
12
13
14/* PIC I/O mapped registers */
15
16#define IRR 0x0 /* Interrupt Request Register */
17#define ISR 0x0 /* In-Service Register */
18#define ICW1 0x0 /* Initialization Control Word 1 */
19#define OCW2 0x0 /* Operation Control Word 2 */
20#define OCW3 0x0 /* Operation Control Word 3 */
21#define ICW2 0x1 /* Initialization Control Word 2 */
22#define ICW3 0x1 /* Initialization Control Word 3 */
23#define ICW4 0x1 /* Initialization Control Word 4 */
24#define IMR 0x1 /* Interrupt Mask Register */
25
26/* bits for IRR, IMR, ISR and ICW3 */
27#define IR7 0x80 /* IR7 */
28#define IR6 0x40 /* IR6 */
29#define IR5 0x20 /* IR5 */
30#define IR4 0x10 /* IR4 */
31#define IR3 0x08 /* IR3 */
32#define IR2 0x04 /* IR2 */
33#define IR1 0x02 /* IR1 */
34#define IR0 0x01 /* IR0 */
35
36/* bits for SEOI */
37#define SEOI_IR7 0x07 /* IR7 */
38#define SEOI_IR6 0x06 /* IR6 */
39#define SEOI_IR5 0x05 /* IR5 */
40#define SEOI_IR4 0x04 /* IR4 */
41#define SEOI_IR3 0x03 /* IR3 */
42#define SEOI_IR2 0x02 /* IR2 */
43#define SEOI_IR1 0x01 /* IR1 */
44#define SEOI_IR0 0x00 /* IR0 */
45
46/* OCW2 bits */
47#define OCW2_RCLR 0x00 /* Rotate/clear */
48#define OCW2_NEOI 0x20 /* Non specific EOI */
49#define OCW2_NOP 0x40 /* NOP */
50#define OCW2_SEOI 0x60 /* Specific EOI */
51#define OCW2_RSET 0x80 /* Rotate/set */
52#define OCW2_REOI 0xA0 /* Rotate on non specific EOI */
53#define OCW2_PSET 0xC0 /* Priority Set Command */
54#define OCW2_RSEOI 0xE0 /* Rotate on specific EOI */
55
56/* ICW1 bits */
57#define ICW1_SEL 0x10 /* Select ICW1 */
58#define ICW1_LTIM 0x08 /* Level-Triggered Interrupt Mode */
59#define ICW1_ADI 0x04 /* Address Interval */
60#define ICW1_SNGL 0x02 /* Single PIC */
61#define ICW1_EICW4 0x01 /* Expect initilization ICW4 */
62
63/* ICW2 is the starting vector number */
64
wdenk8bde7f72003-06-27 21:31:46 +000065/* ICW2 is bit-mask of present slaves for a master device,
wdenk2262cfe2002-11-18 00:14:45 +000066 * or the slave ID for a slave device */
67
68/* ICW4 bits */
69#define ICW4_AEOI 0x02 /* Automatic EOI Mode */
70#define ICW4_PM 0x01 /* Microprocessor Mode */
71
72#endif