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wdenk42d1f032003-10-15 23:53:47 +00001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2002 (440 port)
6 * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
7 *
8 * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
9 * Xianghua Xiao (X.Xiao@motorola.com)
10 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +000012 */
13
14#include <common.h>
15#include <watchdog.h>
16#include <command.h>
17#include <asm/processor.h>
Timur Tabi05f6f662009-08-20 17:41:11 -050018#include <asm/io.h>
John Schmollercc1dd332011-03-10 16:09:26 -060019#ifdef CONFIG_POST
20#include <post.h>
21#endif
wdenk42d1f032003-10-15 23:53:47 +000022
Timur Tabi05f6f662009-08-20 17:41:11 -050023int interrupt_init_cpu(unsigned int *decrementer_count)
wdenk42d1f032003-10-15 23:53:47 +000024{
Kim Phillips680c6132010-08-09 18:39:57 -050025 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
wdenk343117b2005-05-13 22:49:36 +000026
John Schmollercc1dd332011-03-10 16:09:26 -060027#ifdef CONFIG_POST
28 /*
29 * The POST word is stored in the PIC's TFRR register which gets
30 * cleared when the PIC is reset. Save it off so we can restore it
31 * later.
32 */
33 ulong post_word = post_word_load();
34#endif
35
Timur Tabi05f6f662009-08-20 17:41:11 -050036 out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
37 while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
Kumar Gala9cff4442008-08-19 14:46:36 -050038 ;
Timur Tabi05f6f662009-08-20 17:41:11 -050039 out_be32(&pic->gcr, MPC85xx_PICGCR_M);
40 in_be32(&pic->gcr);
Kumar Gala9cff4442008-08-19 14:46:36 -050041
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042 *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
Kumar Gala9cff4442008-08-19 14:46:36 -050043
44 /* PIE is same as DIE, dec interrupt enable */
wdenk343117b2005-05-13 22:49:36 +000045 mtspr(SPRN_TCR, TCR_PIE);
Andy Fleming61a21e92007-08-14 01:34:21 -050046
47#ifdef CONFIG_INTERRUPTS
Andy Fleming534ea6b2008-02-27 15:50:50 -060048 pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
Andrew Klossner52514692008-08-21 07:12:26 -070049 debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1);
Andy Fleming61a21e92007-08-14 01:34:21 -050050
51 pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
Andrew Klossner52514692008-08-21 07:12:26 -070052 debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2);
Andy Fleming61a21e92007-08-14 01:34:21 -050053
54 pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
Andrew Klossner52514692008-08-21 07:12:26 -070055 debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3);
Andy Fleming61a21e92007-08-14 01:34:21 -050056
57#ifdef CONFIG_PCI1
58 pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
Andrew Klossner52514692008-08-21 07:12:26 -070059 debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8);
Andy Fleming61a21e92007-08-14 01:34:21 -050060#endif
61#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
62 pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
Andrew Klossner52514692008-08-21 07:12:26 -070063 debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9);
Andy Fleming61a21e92007-08-14 01:34:21 -050064#endif
65#ifdef CONFIG_PCIE1
66 pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */
Andrew Klossner52514692008-08-21 07:12:26 -070067 debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10);
Andy Fleming61a21e92007-08-14 01:34:21 -050068#endif
69#ifdef CONFIG_PCIE3
70 pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */
Andrew Klossner52514692008-08-21 07:12:26 -070071 debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11);
Andy Fleming61a21e92007-08-14 01:34:21 -050072#endif
73
74 pic->ctpr=0; /* 40080 clear current task priority register */
75#endif
76
John Schmollercc1dd332011-03-10 16:09:26 -060077#ifdef CONFIG_POST
78 post_word_store(post_word);
79#endif
80
wdenk42d1f032003-10-15 23:53:47 +000081 return (0);
82}
83
Kumar Gala9cff4442008-08-19 14:46:36 -050084/* Install and free a interrupt handler. Not implemented yet. */
wdenk42d1f032003-10-15 23:53:47 +000085
86void
87irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
88{
89 return;
90}
91
92void
93irq_free_handler(int vec)
94{
95 return;
96}
97
Kumar Gala9cff4442008-08-19 14:46:36 -050098void timer_interrupt_cpu(struct pt_regs *regs)
wdenk42d1f032003-10-15 23:53:47 +000099{
Kumar Gala9cff4442008-08-19 14:46:36 -0500100 /* PIS is same as DIS, dec interrupt status */
wdenk343117b2005-05-13 22:49:36 +0000101 mtspr(SPRN_TSR, TSR_PIS);
wdenk42d1f032003-10-15 23:53:47 +0000102}
103
Jon Loeliger44312832007-07-09 19:06:00 -0500104#if defined(CONFIG_CMD_IRQ)
Kumar Gala9cff4442008-08-19 14:46:36 -0500105/* irqinfo - print information about PCI devices,not implemented. */
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200106int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenk42d1f032003-10-15 23:53:47 +0000107{
wdenk42d1f032003-10-15 23:53:47 +0000108 return 0;
109}
Jon Loeliger44312832007-07-09 19:06:00 -0500110#endif