wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle |
| 7 | * Copyright (C) 2000 Silicon Graphics, Inc. |
| 8 | * Modified for further R[236]000 support by Paul M. Antoine, 1996. |
| 9 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 10 | * Copyright (C) 2000, 07 MIPS Technologies, Inc. |
| 11 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 12 | */ |
| 13 | #ifndef _ASM_MIPSREGS_H |
| 14 | #define _ASM_MIPSREGS_H |
| 15 | |
| 16 | #if 0 |
| 17 | #include <linux/linkage.h> |
| 18 | #endif |
| 19 | |
| 20 | /* |
| 21 | * The following macros are especially useful for __asm__ |
| 22 | * inline assembler. |
| 23 | */ |
| 24 | #ifndef __STR |
| 25 | #define __STR(x) #x |
| 26 | #endif |
| 27 | #ifndef STR |
| 28 | #define STR(x) __STR(x) |
| 29 | #endif |
| 30 | |
| 31 | /* |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 32 | * Configure language |
| 33 | */ |
| 34 | #ifdef __ASSEMBLY__ |
| 35 | #define _ULCAST_ |
| 36 | #else |
| 37 | #define _ULCAST_ (unsigned long) |
| 38 | #endif |
| 39 | |
| 40 | /* |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 41 | * Coprocessor 0 register names |
| 42 | */ |
| 43 | #define CP0_INDEX $0 |
| 44 | #define CP0_RANDOM $1 |
| 45 | #define CP0_ENTRYLO0 $2 |
| 46 | #define CP0_ENTRYLO1 $3 |
| 47 | #define CP0_CONF $3 |
| 48 | #define CP0_CONTEXT $4 |
| 49 | #define CP0_PAGEMASK $5 |
| 50 | #define CP0_WIRED $6 |
| 51 | #define CP0_INFO $7 |
| 52 | #define CP0_BADVADDR $8 |
| 53 | #define CP0_COUNT $9 |
| 54 | #define CP0_ENTRYHI $10 |
| 55 | #define CP0_COMPARE $11 |
| 56 | #define CP0_STATUS $12 |
| 57 | #define CP0_CAUSE $13 |
| 58 | #define CP0_EPC $14 |
| 59 | #define CP0_PRID $15 |
| 60 | #define CP0_CONFIG $16 |
| 61 | #define CP0_LLADDR $17 |
| 62 | #define CP0_WATCHLO $18 |
| 63 | #define CP0_WATCHHI $19 |
| 64 | #define CP0_XCONTEXT $20 |
| 65 | #define CP0_FRAMEMASK $21 |
| 66 | #define CP0_DIAGNOSTIC $22 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 67 | #define CP0_DEBUG $23 |
| 68 | #define CP0_DEPC $24 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 69 | #define CP0_PERFORMANCE $25 |
| 70 | #define CP0_ECC $26 |
| 71 | #define CP0_CACHEERR $27 |
| 72 | #define CP0_TAGLO $28 |
| 73 | #define CP0_TAGHI $29 |
| 74 | #define CP0_ERROREPC $30 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 75 | #define CP0_DESAVE $31 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * R4640/R4650 cp0 register names. These registers are listed |
| 79 | * here only for completeness; without MMU these CPUs are not useable |
| 80 | * by Linux. A future ELKS port might take make Linux run on them |
| 81 | * though ... |
| 82 | */ |
| 83 | #define CP0_IBASE $0 |
| 84 | #define CP0_IBOUND $1 |
| 85 | #define CP0_DBASE $2 |
| 86 | #define CP0_DBOUND $3 |
| 87 | #define CP0_CALG $17 |
| 88 | #define CP0_IWATCH $18 |
| 89 | #define CP0_DWATCH $19 |
| 90 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 91 | /* |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 92 | * Coprocessor 0 Set 1 register names |
| 93 | */ |
| 94 | #define CP0_S1_DERRADDR0 $26 |
| 95 | #define CP0_S1_DERRADDR1 $27 |
| 96 | #define CP0_S1_INTCONTROL $20 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 97 | |
| 98 | /* |
| 99 | * Coprocessor 0 Set 2 register names |
| 100 | */ |
| 101 | #define CP0_S2_SRSCTL $12 /* MIPSR2 */ |
| 102 | |
| 103 | /* |
| 104 | * Coprocessor 0 Set 3 register names |
| 105 | */ |
| 106 | #define CP0_S3_SRSMAP $12 /* MIPSR2 */ |
| 107 | |
| 108 | /* |
| 109 | * TX39 Series |
| 110 | */ |
| 111 | #define CP0_TX39_CACHE $7 |
| 112 | |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 113 | /* |
| 114 | * Coprocessor 1 (FPU) register names |
| 115 | */ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 116 | #define CP1_REVISION $0 |
| 117 | #define CP1_STATUS $31 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 118 | |
| 119 | /* |
| 120 | * FPU Status Register Values |
| 121 | */ |
| 122 | /* |
| 123 | * Status Register Values |
| 124 | */ |
| 125 | |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 126 | #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ |
| 127 | #define FPU_CSR_COND 0x00800000 /* $fcc0 */ |
| 128 | #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ |
| 129 | #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ |
| 130 | #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ |
| 131 | #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ |
| 132 | #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ |
| 133 | #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ |
| 134 | #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ |
| 135 | #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 136 | |
| 137 | /* |
| 138 | * X the exception cause indicator |
| 139 | * E the exception enable |
| 140 | * S the sticky/flag bit |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 141 | */ |
| 142 | #define FPU_CSR_ALL_X 0x0003f000 |
| 143 | #define FPU_CSR_UNI_X 0x00020000 |
| 144 | #define FPU_CSR_INV_X 0x00010000 |
| 145 | #define FPU_CSR_DIV_X 0x00008000 |
| 146 | #define FPU_CSR_OVF_X 0x00004000 |
| 147 | #define FPU_CSR_UDF_X 0x00002000 |
| 148 | #define FPU_CSR_INE_X 0x00001000 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 149 | |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 150 | #define FPU_CSR_ALL_E 0x00000f80 |
| 151 | #define FPU_CSR_INV_E 0x00000800 |
| 152 | #define FPU_CSR_DIV_E 0x00000400 |
| 153 | #define FPU_CSR_OVF_E 0x00000200 |
| 154 | #define FPU_CSR_UDF_E 0x00000100 |
| 155 | #define FPU_CSR_INE_E 0x00000080 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 156 | |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 157 | #define FPU_CSR_ALL_S 0x0000007c |
| 158 | #define FPU_CSR_INV_S 0x00000040 |
| 159 | #define FPU_CSR_DIV_S 0x00000020 |
| 160 | #define FPU_CSR_OVF_S 0x00000010 |
| 161 | #define FPU_CSR_UDF_S 0x00000008 |
| 162 | #define FPU_CSR_INE_S 0x00000004 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 163 | |
| 164 | /* rounding mode */ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 165 | #define FPU_CSR_RN 0x0 /* nearest */ |
| 166 | #define FPU_CSR_RZ 0x1 /* towards zero */ |
| 167 | #define FPU_CSR_RU 0x2 /* towards +Infinity */ |
| 168 | #define FPU_CSR_RD 0x3 /* towards -Infinity */ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 169 | |
| 170 | /* |
| 171 | * Values for PageMask register |
| 172 | */ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 173 | #ifdef CONFIG_CPU_VR41XX |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 174 | |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 175 | /* Why doesn't stupidity hurt ... */ |
| 176 | |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 177 | #define PM_1K 0x00000000 |
| 178 | #define PM_4K 0x00001800 |
| 179 | #define PM_16K 0x00007800 |
| 180 | #define PM_64K 0x0001f800 |
| 181 | #define PM_256K 0x0007f800 |
| 182 | |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 183 | #else |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 184 | |
| 185 | #define PM_4K 0x00000000 |
| 186 | #define PM_16K 0x00006000 |
| 187 | #define PM_64K 0x0001e000 |
| 188 | #define PM_256K 0x0007e000 |
| 189 | #define PM_1M 0x001fe000 |
| 190 | #define PM_4M 0x007fe000 |
| 191 | #define PM_16M 0x01ffe000 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 192 | #define PM_64M 0x07ffe000 |
| 193 | #define PM_256M 0x1fffe000 |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 194 | |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 195 | #endif |
| 196 | |
| 197 | /* |
| 198 | * Values used for computation of new tlb entries |
| 199 | */ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 200 | #define PL_4K 12 |
| 201 | #define PL_16K 14 |
| 202 | #define PL_64K 16 |
| 203 | #define PL_256K 18 |
| 204 | #define PL_1M 20 |
| 205 | #define PL_4M 22 |
| 206 | #define PL_16M 24 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 207 | #define PL_64M 26 |
| 208 | #define PL_256M 28 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 209 | |
| 210 | /* |
| 211 | * Macros to access the system control coprocessor |
| 212 | */ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 213 | #define read_32bit_cp0_register(source) \ |
| 214 | ({ int __res; \ |
| 215 | __asm__ __volatile__( \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 216 | ".set\tpush\n\t" \ |
| 217 | ".set\treorder\n\t" \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 218 | "mfc0\t%0,"STR(source)"\n\t" \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 219 | ".set\tpop" \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 220 | : "=r" (__res)); \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 221 | __res;}) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 222 | |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 223 | #define read_32bit_cp0_set1_register(source) \ |
| 224 | ({ int __res; \ |
| 225 | __asm__ __volatile__( \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 226 | ".set\tpush\n\t" \ |
| 227 | ".set\treorder\n\t" \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 228 | "cfc0\t%0,"STR(source)"\n\t" \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 229 | ".set\tpop" \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 230 | : "=r" (__res)); \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 231 | __res;}) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 232 | |
| 233 | /* |
| 234 | * For now use this only with interrupts disabled! |
| 235 | */ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 236 | #define read_64bit_cp0_register(source) \ |
| 237 | ({ int __res; \ |
| 238 | __asm__ __volatile__( \ |
| 239 | ".set\tmips3\n\t" \ |
| 240 | "dmfc0\t%0,"STR(source)"\n\t" \ |
| 241 | ".set\tmips0" \ |
| 242 | : "=r" (__res)); \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 243 | __res;}) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 244 | |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 245 | #define write_32bit_cp0_register(register,value) \ |
| 246 | __asm__ __volatile__( \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 247 | "mtc0\t%0,"STR(register)"\n\t" \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 248 | "nop" \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 249 | : : "r" (value)); |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 250 | |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 251 | #define write_32bit_cp0_set1_register(register,value) \ |
| 252 | __asm__ __volatile__( \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 253 | "ctc0\t%0,"STR(register)"\n\t" \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 254 | "nop" \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 255 | : : "r" (value)); |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 256 | |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 257 | #define write_64bit_cp0_register(register,value) \ |
| 258 | __asm__ __volatile__( \ |
| 259 | ".set\tmips3\n\t" \ |
| 260 | "dmtc0\t%0,"STR(register)"\n\t" \ |
| 261 | ".set\tmips0" \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 262 | : : "r" (value)) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 263 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 264 | /* |
| 265 | * This should be changed when we get a compiler that support the MIPS32 ISA. |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 266 | */ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 267 | #define read_mips32_cp0_config1() \ |
| 268 | ({ int __res; \ |
| 269 | __asm__ __volatile__( \ |
| 270 | ".set\tnoreorder\n\t" \ |
| 271 | ".set\tnoat\n\t" \ |
| 272 | ".word\t0x40018001\n\t" \ |
| 273 | "move\t%0,$1\n\t" \ |
| 274 | ".set\tat\n\t" \ |
| 275 | ".set\treorder" \ |
| 276 | :"=r" (__res)); \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 277 | __res;}) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 278 | |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 279 | #define tlb_write_indexed() \ |
| 280 | __asm__ __volatile__( \ |
| 281 | ".set noreorder\n\t" \ |
| 282 | "tlbwi\n\t" \ |
wdenk | 5da627a | 2003-10-09 20:09:04 +0000 | [diff] [blame] | 283 | ".set reorder") |
| 284 | |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 285 | /* |
| 286 | * R4x00 interrupt enable / cause bits |
| 287 | */ |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 288 | #define IE_SW0 (_ULCAST_(1) << 8) |
| 289 | #define IE_SW1 (_ULCAST_(1) << 9) |
| 290 | #define IE_IRQ0 (_ULCAST_(1) << 10) |
| 291 | #define IE_IRQ1 (_ULCAST_(1) << 11) |
| 292 | #define IE_IRQ2 (_ULCAST_(1) << 12) |
| 293 | #define IE_IRQ3 (_ULCAST_(1) << 13) |
| 294 | #define IE_IRQ4 (_ULCAST_(1) << 14) |
| 295 | #define IE_IRQ5 (_ULCAST_(1) << 15) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 296 | |
| 297 | /* |
| 298 | * R4x00 interrupt cause bits |
| 299 | */ |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 300 | #define C_SW0 (_ULCAST_(1) << 8) |
| 301 | #define C_SW1 (_ULCAST_(1) << 9) |
| 302 | #define C_IRQ0 (_ULCAST_(1) << 10) |
| 303 | #define C_IRQ1 (_ULCAST_(1) << 11) |
| 304 | #define C_IRQ2 (_ULCAST_(1) << 12) |
| 305 | #define C_IRQ3 (_ULCAST_(1) << 13) |
| 306 | #define C_IRQ4 (_ULCAST_(1) << 14) |
| 307 | #define C_IRQ5 (_ULCAST_(1) << 15) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 308 | |
| 309 | #ifndef _LANGUAGE_ASSEMBLY |
| 310 | /* |
| 311 | * Manipulate the status register. |
| 312 | * Mostly used to access the interrupt bits. |
| 313 | */ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 314 | #define __BUILD_SET_CP0(name,register) \ |
| 315 | extern __inline__ unsigned int \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 316 | set_cp0_##name(unsigned int set) \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 317 | { \ |
| 318 | unsigned int res; \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 319 | \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 320 | res = read_32bit_cp0_register(register); \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 321 | res |= set; \ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 322 | write_32bit_cp0_register(register, res); \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 323 | \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 324 | return res; \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 325 | } \ |
| 326 | \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 327 | extern __inline__ unsigned int \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 328 | clear_cp0_##name(unsigned int clear) \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 329 | { \ |
| 330 | unsigned int res; \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 331 | \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 332 | res = read_32bit_cp0_register(register); \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 333 | res &= ~clear; \ |
| 334 | write_32bit_cp0_register(register, res); \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 335 | \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 336 | return res; \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 337 | } \ |
| 338 | \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 339 | extern __inline__ unsigned int \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 340 | change_cp0_##name(unsigned int change, unsigned int new) \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 341 | { \ |
| 342 | unsigned int res; \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 343 | \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 344 | res = read_32bit_cp0_register(register); \ |
| 345 | res &= ~change; \ |
| 346 | res |= (new & change); \ |
| 347 | if(change) \ |
| 348 | write_32bit_cp0_register(register, res); \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 349 | \ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 350 | return res; \ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 351 | } |
| 352 | |
| 353 | __BUILD_SET_CP0(status,CP0_STATUS) |
| 354 | __BUILD_SET_CP0(cause,CP0_CAUSE) |
| 355 | __BUILD_SET_CP0(config,CP0_CONFIG) |
| 356 | |
| 357 | #endif /* defined (_LANGUAGE_ASSEMBLY) */ |
| 358 | |
| 359 | /* |
| 360 | * Bitfields in the R4xx0 cp0 status register |
| 361 | */ |
| 362 | #define ST0_IE 0x00000001 |
| 363 | #define ST0_EXL 0x00000002 |
| 364 | #define ST0_ERL 0x00000004 |
| 365 | #define ST0_KSU 0x00000018 |
| 366 | # define KSU_USER 0x00000010 |
| 367 | # define KSU_SUPERVISOR 0x00000008 |
| 368 | # define KSU_KERNEL 0x00000000 |
| 369 | #define ST0_UX 0x00000020 |
| 370 | #define ST0_SX 0x00000040 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 371 | #define ST0_KX 0x00000080 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 372 | #define ST0_DE 0x00010000 |
| 373 | #define ST0_CE 0x00020000 |
| 374 | |
| 375 | /* |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 376 | * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate |
| 377 | * cacheops in userspace. This bit exists only on RM7000 and RM9000 |
| 378 | * processors. |
| 379 | */ |
| 380 | #define ST0_CO 0x08000000 |
| 381 | |
| 382 | /* |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 383 | * Bitfields in the R[23]000 cp0 status register. |
| 384 | */ |
Shinya Kuribayashi | bf462ae | 2008-05-30 00:53:37 +0900 | [diff] [blame] | 385 | #define ST0_IEC 0x00000001 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 386 | #define ST0_KUC 0x00000002 |
| 387 | #define ST0_IEP 0x00000004 |
| 388 | #define ST0_KUP 0x00000008 |
| 389 | #define ST0_IEO 0x00000010 |
| 390 | #define ST0_KUO 0x00000020 |
| 391 | /* bits 6 & 7 are reserved on R[23]000 */ |
| 392 | #define ST0_ISC 0x00010000 |
| 393 | #define ST0_SWC 0x00020000 |
| 394 | #define ST0_CM 0x00080000 |
| 395 | |
| 396 | /* |
| 397 | * Bits specific to the R4640/R4650 |
| 398 | */ |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 399 | #define ST0_UM (_ULCAST_(1) << 4) |
| 400 | #define ST0_IL (_ULCAST_(1) << 23) |
| 401 | #define ST0_DL (_ULCAST_(1) << 24) |
| 402 | |
| 403 | /* |
| 404 | * Enable the MIPS MDMX and DSP ASEs |
| 405 | */ |
| 406 | #define ST0_MX 0x01000000 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 407 | |
| 408 | /* |
| 409 | * Bitfields in the TX39 family CP0 Configuration Register 3 |
| 410 | */ |
| 411 | #define TX39_CONF_ICS_SHIFT 19 |
| 412 | #define TX39_CONF_ICS_MASK 0x00380000 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 413 | #define TX39_CONF_ICS_1KB 0x00000000 |
| 414 | #define TX39_CONF_ICS_2KB 0x00080000 |
| 415 | #define TX39_CONF_ICS_4KB 0x00100000 |
| 416 | #define TX39_CONF_ICS_8KB 0x00180000 |
| 417 | #define TX39_CONF_ICS_16KB 0x00200000 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 418 | |
| 419 | #define TX39_CONF_DCS_SHIFT 16 |
| 420 | #define TX39_CONF_DCS_MASK 0x00070000 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 421 | #define TX39_CONF_DCS_1KB 0x00000000 |
| 422 | #define TX39_CONF_DCS_2KB 0x00010000 |
| 423 | #define TX39_CONF_DCS_4KB 0x00020000 |
| 424 | #define TX39_CONF_DCS_8KB 0x00030000 |
| 425 | #define TX39_CONF_DCS_16KB 0x00040000 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 426 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 427 | #define TX39_CONF_CWFON 0x00004000 |
| 428 | #define TX39_CONF_WBON 0x00002000 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 429 | #define TX39_CONF_RF_SHIFT 10 |
| 430 | #define TX39_CONF_RF_MASK 0x00000c00 |
| 431 | #define TX39_CONF_DOZE 0x00000200 |
| 432 | #define TX39_CONF_HALT 0x00000100 |
| 433 | #define TX39_CONF_LOCK 0x00000080 |
| 434 | #define TX39_CONF_ICE 0x00000020 |
| 435 | #define TX39_CONF_DCE 0x00000010 |
| 436 | #define TX39_CONF_IRSIZE_SHIFT 2 |
| 437 | #define TX39_CONF_IRSIZE_MASK 0x0000000c |
| 438 | #define TX39_CONF_DRSIZE_SHIFT 0 |
| 439 | #define TX39_CONF_DRSIZE_MASK 0x00000003 |
| 440 | |
| 441 | /* |
| 442 | * Status register bits available in all MIPS CPUs. |
| 443 | */ |
| 444 | #define ST0_IM 0x0000ff00 |
| 445 | #define STATUSB_IP0 8 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 446 | #define STATUSF_IP0 (_ULCAST_(1) << 8) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 447 | #define STATUSB_IP1 9 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 448 | #define STATUSF_IP1 (_ULCAST_(1) << 9) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 449 | #define STATUSB_IP2 10 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 450 | #define STATUSF_IP2 (_ULCAST_(1) << 10) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 451 | #define STATUSB_IP3 11 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 452 | #define STATUSF_IP3 (_ULCAST_(1) << 11) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 453 | #define STATUSB_IP4 12 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 454 | #define STATUSF_IP4 (_ULCAST_(1) << 12) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 455 | #define STATUSB_IP5 13 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 456 | #define STATUSF_IP5 (_ULCAST_(1) << 13) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 457 | #define STATUSB_IP6 14 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 458 | #define STATUSF_IP6 (_ULCAST_(1) << 14) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 459 | #define STATUSB_IP7 15 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 460 | #define STATUSF_IP7 (_ULCAST_(1) << 15) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 461 | #define STATUSB_IP8 0 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 462 | #define STATUSF_IP8 (_ULCAST_(1) << 0) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 463 | #define STATUSB_IP9 1 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 464 | #define STATUSF_IP9 (_ULCAST_(1) << 1) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 465 | #define STATUSB_IP10 2 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 466 | #define STATUSF_IP10 (_ULCAST_(1) << 2) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 467 | #define STATUSB_IP11 3 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 468 | #define STATUSF_IP11 (_ULCAST_(1) << 3) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 469 | #define STATUSB_IP12 4 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 470 | #define STATUSF_IP12 (_ULCAST_(1) << 4) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 471 | #define STATUSB_IP13 5 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 472 | #define STATUSF_IP13 (_ULCAST_(1) << 5) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 473 | #define STATUSB_IP14 6 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 474 | #define STATUSF_IP14 (_ULCAST_(1) << 6) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 475 | #define STATUSB_IP15 7 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 476 | #define STATUSF_IP15 (_ULCAST_(1) << 7) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 477 | #define ST0_CH 0x00040000 |
| 478 | #define ST0_SR 0x00100000 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 479 | #define ST0_TS 0x00200000 |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 480 | #define ST0_BEV 0x00400000 |
| 481 | #define ST0_RE 0x02000000 |
| 482 | #define ST0_FR 0x04000000 |
| 483 | #define ST0_CU 0xf0000000 |
| 484 | #define ST0_CU0 0x10000000 |
| 485 | #define ST0_CU1 0x20000000 |
| 486 | #define ST0_CU2 0x40000000 |
| 487 | #define ST0_CU3 0x80000000 |
| 488 | #define ST0_XX 0x80000000 /* MIPS IV naming */ |
| 489 | |
| 490 | /* |
| 491 | * Bitfields and bit numbers in the coprocessor 0 cause register. |
| 492 | * |
| 493 | * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. |
| 494 | */ |
| 495 | #define CAUSEB_EXCCODE 2 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 496 | #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 497 | #define CAUSEB_IP 8 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 498 | #define CAUSEF_IP (_ULCAST_(255) << 8) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 499 | #define CAUSEB_IP0 8 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 500 | #define CAUSEF_IP0 (_ULCAST_(1) << 8) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 501 | #define CAUSEB_IP1 9 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 502 | #define CAUSEF_IP1 (_ULCAST_(1) << 9) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 503 | #define CAUSEB_IP2 10 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 504 | #define CAUSEF_IP2 (_ULCAST_(1) << 10) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 505 | #define CAUSEB_IP3 11 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 506 | #define CAUSEF_IP3 (_ULCAST_(1) << 11) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 507 | #define CAUSEB_IP4 12 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 508 | #define CAUSEF_IP4 (_ULCAST_(1) << 12) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 509 | #define CAUSEB_IP5 13 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 510 | #define CAUSEF_IP5 (_ULCAST_(1) << 13) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 511 | #define CAUSEB_IP6 14 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 512 | #define CAUSEF_IP6 (_ULCAST_(1) << 14) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 513 | #define CAUSEB_IP7 15 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 514 | #define CAUSEF_IP7 (_ULCAST_(1) << 15) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 515 | #define CAUSEB_IV 23 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 516 | #define CAUSEF_IV (_ULCAST_(1) << 23) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 517 | #define CAUSEB_CE 28 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 518 | #define CAUSEF_CE (_ULCAST_(3) << 28) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 519 | #define CAUSEB_BD 31 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 520 | #define CAUSEF_BD (_ULCAST_(1) << 31) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 521 | |
| 522 | /* |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 523 | * Bits in the coprocessor 0 config register. |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 524 | */ |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 525 | /* Generic bits. */ |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 526 | #define CONF_CM_CACHABLE_NO_WA 0 |
| 527 | #define CONF_CM_CACHABLE_WA 1 |
| 528 | #define CONF_CM_UNCACHED 2 |
| 529 | #define CONF_CM_CACHABLE_NONCOHERENT 3 |
| 530 | #define CONF_CM_CACHABLE_CE 4 |
| 531 | #define CONF_CM_CACHABLE_COW 5 |
| 532 | #define CONF_CM_CACHABLE_CUW 6 |
| 533 | #define CONF_CM_CACHABLE_ACCELERATED 7 |
| 534 | #define CONF_CM_CMASK 7 |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 535 | #define CONF_BE (_ULCAST_(1) << 15) |
| 536 | |
| 537 | /* Bits common to various processors. */ |
| 538 | #define CONF_CU (_ULCAST_(1) << 3) |
| 539 | #define CONF_DB (_ULCAST_(1) << 4) |
| 540 | #define CONF_IB (_ULCAST_(1) << 5) |
| 541 | #define CONF_DC (_ULCAST_(7) << 6) |
| 542 | #define CONF_IC (_ULCAST_(7) << 9) |
| 543 | #define CONF_EB (_ULCAST_(1) << 13) |
| 544 | #define CONF_EM (_ULCAST_(1) << 14) |
| 545 | #define CONF_SM (_ULCAST_(1) << 16) |
| 546 | #define CONF_SC (_ULCAST_(1) << 17) |
| 547 | #define CONF_EW (_ULCAST_(3) << 18) |
| 548 | #define CONF_EP (_ULCAST_(15)<< 24) |
| 549 | #define CONF_EC (_ULCAST_(7) << 28) |
| 550 | #define CONF_CM (_ULCAST_(1) << 31) |
| 551 | |
| 552 | /* Bits specific to the R4xx0. */ |
| 553 | #define R4K_CONF_SW (_ULCAST_(1) << 20) |
| 554 | #define R4K_CONF_SS (_ULCAST_(1) << 21) |
| 555 | #define R4K_CONF_SB (_ULCAST_(3) << 22) |
| 556 | |
| 557 | /* Bits specific to the R5000. */ |
| 558 | #define R5K_CONF_SE (_ULCAST_(1) << 12) |
| 559 | #define R5K_CONF_SS (_ULCAST_(3) << 20) |
| 560 | |
| 561 | /* Bits specific to the RM7000. */ |
| 562 | #define RM7K_CONF_SE (_ULCAST_(1) << 3) |
| 563 | #define RM7K_CONF_TE (_ULCAST_(1) << 12) |
| 564 | #define RM7K_CONF_CLK (_ULCAST_(1) << 16) |
| 565 | #define RM7K_CONF_TC (_ULCAST_(1) << 17) |
| 566 | #define RM7K_CONF_SI (_ULCAST_(3) << 20) |
| 567 | #define RM7K_CONF_SC (_ULCAST_(1) << 31) |
| 568 | |
| 569 | /* Bits specific to the R10000. */ |
| 570 | #define R10K_CONF_DN (_ULCAST_(3) << 3) |
| 571 | #define R10K_CONF_CT (_ULCAST_(1) << 5) |
| 572 | #define R10K_CONF_PE (_ULCAST_(1) << 6) |
| 573 | #define R10K_CONF_PM (_ULCAST_(3) << 7) |
| 574 | #define R10K_CONF_EC (_ULCAST_(15)<< 9) |
| 575 | #define R10K_CONF_SB (_ULCAST_(1) << 13) |
| 576 | #define R10K_CONF_SK (_ULCAST_(1) << 14) |
| 577 | #define R10K_CONF_SS (_ULCAST_(7) << 16) |
| 578 | #define R10K_CONF_SC (_ULCAST_(7) << 19) |
| 579 | #define R10K_CONF_DC (_ULCAST_(7) << 26) |
| 580 | #define R10K_CONF_IC (_ULCAST_(7) << 29) |
| 581 | |
| 582 | /* Bits specific to the VR41xx. */ |
| 583 | #define VR41_CONF_CS (_ULCAST_(1) << 12) |
| 584 | #define VR41_CONF_P4K (_ULCAST_(1) << 13) |
| 585 | #define VR41_CONF_BP (_ULCAST_(1) << 16) |
| 586 | #define VR41_CONF_M16 (_ULCAST_(1) << 20) |
| 587 | #define VR41_CONF_AD (_ULCAST_(1) << 23) |
| 588 | |
| 589 | /* Bits specific to the R30xx. */ |
| 590 | #define R30XX_CONF_FDM (_ULCAST_(1) << 19) |
| 591 | #define R30XX_CONF_REV (_ULCAST_(1) << 22) |
| 592 | #define R30XX_CONF_AC (_ULCAST_(1) << 23) |
| 593 | #define R30XX_CONF_RF (_ULCAST_(1) << 24) |
| 594 | #define R30XX_CONF_HALT (_ULCAST_(1) << 25) |
| 595 | #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) |
| 596 | #define R30XX_CONF_DBR (_ULCAST_(1) << 29) |
| 597 | #define R30XX_CONF_SB (_ULCAST_(1) << 30) |
| 598 | #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) |
| 599 | |
| 600 | /* Bits specific to the TX49. */ |
| 601 | #define TX49_CONF_DC (_ULCAST_(1) << 16) |
| 602 | #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ |
| 603 | #define TX49_CONF_HALT (_ULCAST_(1) << 18) |
| 604 | #define TX49_CONF_CWFON (_ULCAST_(1) << 27) |
| 605 | |
| 606 | /* Bits specific to the MIPS32/64 PRA. */ |
| 607 | #define MIPS_CONF_MT (_ULCAST_(7) << 7) |
| 608 | #define MIPS_CONF_AR (_ULCAST_(7) << 10) |
| 609 | #define MIPS_CONF_AT (_ULCAST_(3) << 13) |
| 610 | #define MIPS_CONF_M (_ULCAST_(1) << 31) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 611 | |
| 612 | /* |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 613 | * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 614 | */ |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 615 | #define MIPS_CONF1_FP (_ULCAST_(1) << 0) |
| 616 | #define MIPS_CONF1_EP (_ULCAST_(1) << 1) |
| 617 | #define MIPS_CONF1_CA (_ULCAST_(1) << 2) |
| 618 | #define MIPS_CONF1_WR (_ULCAST_(1) << 3) |
| 619 | #define MIPS_CONF1_PC (_ULCAST_(1) << 4) |
| 620 | #define MIPS_CONF1_MD (_ULCAST_(1) << 5) |
| 621 | #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) |
| 622 | #define MIPS_CONF1_DA (_ULCAST_(7) << 7) |
| 623 | #define MIPS_CONF1_DL (_ULCAST_(7) << 10) |
| 624 | #define MIPS_CONF1_DS (_ULCAST_(7) << 13) |
| 625 | #define MIPS_CONF1_IA (_ULCAST_(7) << 16) |
| 626 | #define MIPS_CONF1_IL (_ULCAST_(7) << 19) |
| 627 | #define MIPS_CONF1_IS (_ULCAST_(7) << 22) |
| 628 | #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) |
| 629 | |
| 630 | #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) |
| 631 | #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) |
| 632 | #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) |
| 633 | #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) |
| 634 | #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) |
| 635 | #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) |
| 636 | #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) |
| 637 | #define MIPS_CONF2_TU (_ULCAST_(7) << 28) |
| 638 | |
| 639 | #define MIPS_CONF3_TL (_ULCAST_(1) << 0) |
| 640 | #define MIPS_CONF3_SM (_ULCAST_(1) << 1) |
| 641 | #define MIPS_CONF3_MT (_ULCAST_(1) << 2) |
| 642 | #define MIPS_CONF3_SP (_ULCAST_(1) << 4) |
| 643 | #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) |
| 644 | #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) |
| 645 | #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) |
| 646 | #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) |
| 647 | #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) |
| 648 | |
| 649 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) |
| 650 | |
| 651 | #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 652 | |
| 653 | /* |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 654 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 655 | */ |
Shinya Kuribayashi | 1a3adac | 2008-05-30 00:53:38 +0900 | [diff] [blame^] | 656 | #define MIPS_FPIR_S (_ULCAST_(1) << 16) |
| 657 | #define MIPS_FPIR_D (_ULCAST_(1) << 17) |
| 658 | #define MIPS_FPIR_PS (_ULCAST_(1) << 18) |
| 659 | #define MIPS_FPIR_3D (_ULCAST_(1) << 19) |
| 660 | #define MIPS_FPIR_W (_ULCAST_(1) << 20) |
| 661 | #define MIPS_FPIR_L (_ULCAST_(1) << 21) |
| 662 | #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) |
wdenk | 6069ff2 | 2003-02-28 00:49:47 +0000 | [diff] [blame] | 663 | |
| 664 | #endif /* _ASM_MIPSREGS_H */ |