Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Marius Groeger <mgroeger@sysgo.de> |
| 5 | * |
| 6 | * (C) Copyright 2002 |
| 7 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
| 8 | * |
| 9 | * (C) Copyright 2005 |
| 10 | * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> |
| 11 | * |
| 12 | * See file CREDITS for list of people who contributed to this |
| 13 | * project. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or |
| 16 | * modify it under the terms of the GNU General Public License as |
| 17 | * published by the Free Software Foundation; either version 2 of |
| 18 | * the License, or (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 28 | * MA 02111-1307 USA |
| 29 | */ |
| 30 | |
| 31 | #include <common.h> |
Ben Warren | b1c0eaa | 2009-08-25 13:09:37 -0700 | [diff] [blame] | 32 | #include <netdev.h> |
kevin.morfitt@fearnside-systems.co.uk | ac67804 | 2009-11-17 18:30:34 +0900 | [diff] [blame] | 33 | #include <asm/arch/s3c24x0_cpu.h> |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 34 | |
Jon Loeliger | ab3abcb | 2007-07-09 18:45:16 -0500 | [diff] [blame] | 35 | #if defined(CONFIG_CMD_NAND) |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 36 | #include <linux/mtd/nand.h> |
| 37 | #endif |
| 38 | |
Wolfgang Denk | 1218abf | 2007-09-15 20:48:41 +0200 | [diff] [blame] | 39 | DECLARE_GLOBAL_DATA_PTR; |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 40 | |
| 41 | #define FCLK_SPEED 1 |
| 42 | |
| 43 | #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ |
| 44 | #define M_MDIV 0xC3 |
| 45 | #define M_PDIV 0x4 |
| 46 | #define M_SDIV 0x1 |
| 47 | #elif FCLK_SPEED==1 /* Fout = 202.8MHz */ |
| 48 | #define M_MDIV 0x5c |
| 49 | #define M_PDIV 0x4 |
| 50 | #define M_SDIV 0x0 |
| 51 | #endif |
| 52 | |
| 53 | #define USB_CLOCK 1 |
| 54 | |
| 55 | #if USB_CLOCK==0 |
| 56 | #define U_M_MDIV 0xA1 |
| 57 | #define U_M_PDIV 0x3 |
| 58 | #define U_M_SDIV 0x1 |
| 59 | #elif USB_CLOCK==1 |
| 60 | #define U_M_MDIV 0x48 |
| 61 | #define U_M_PDIV 0x3 |
| 62 | #define U_M_SDIV 0x2 |
| 63 | #endif |
| 64 | |
| 65 | static inline void delay (unsigned long loops) |
| 66 | { |
| 67 | __asm__ volatile ("1:\n" |
| 68 | "subs %0, %1, #1\n" |
| 69 | "bne 1b":"=r" (loops):"0" (loops)); |
| 70 | } |
| 71 | |
| 72 | /* |
| 73 | * Miscellaneous platform dependent initialisations |
| 74 | */ |
| 75 | |
| 76 | int board_init (void) |
| 77 | { |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 78 | struct s3c24x0_clock_power * const clk_power = |
| 79 | s3c24x0_get_base_clock_power(); |
| 80 | struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 81 | |
| 82 | /* to reduce PLL lock time, adjust the LOCKTIME register */ |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 83 | clk_power->locktime = 0xFFFFFF; |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 84 | |
| 85 | /* configure MPLL */ |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 86 | clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 87 | |
| 88 | /* some delay between MPLL and UPLL */ |
| 89 | delay (4000); |
| 90 | |
| 91 | /* configure UPLL */ |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 92 | clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 93 | |
| 94 | /* some delay between MPLL and UPLL */ |
| 95 | delay (8000); |
| 96 | |
| 97 | /* set up the I/O ports */ |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 98 | gpio->gpacon = 0x007FFFFF; |
| 99 | gpio->gpbcon = 0x00044556; |
| 100 | gpio->gpbup = 0x000007FF; |
| 101 | gpio->gpccon = 0xAAAAAAAA; |
| 102 | gpio->gpcup = 0x0000FFFF; |
| 103 | gpio->gpdcon = 0xAAAAAAAA; |
| 104 | gpio->gpdup = 0x0000FFFF; |
| 105 | gpio->gpecon = 0xAAAAAAAA; |
| 106 | gpio->gpeup = 0x0000FFFF; |
| 107 | gpio->gpfcon = 0x000055AA; |
| 108 | gpio->gpfup = 0x000000FF; |
| 109 | gpio->gpgcon = 0xFF95FF3A; |
| 110 | gpio->gpgup = 0x0000FFFF; |
| 111 | gpio->gphcon = 0x0016FAAA; |
| 112 | gpio->gphup = 0x000007FF; |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 113 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 114 | gpio->extint0 = 0x22222222; |
| 115 | gpio->extint1 = 0x22222222; |
| 116 | gpio->extint2 = 0x22222222; |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 117 | |
| 118 | /* arch number of SMDK2410-Board */ |
| 119 | gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; |
| 120 | |
| 121 | /* adress of boot parameters */ |
| 122 | gd->bd->bi_boot_params = 0x30000100; |
| 123 | |
| 124 | icache_enable(); |
| 125 | dcache_enable(); |
| 126 | |
| 127 | return 0; |
| 128 | } |
| 129 | |
| 130 | int dram_init (void) |
| 131 | { |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 132 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 133 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
| 134 | |
| 135 | return 0; |
| 136 | } |
| 137 | |
Jon Loeliger | ab3abcb | 2007-07-09 18:45:16 -0500 | [diff] [blame] | 138 | #if defined(CONFIG_CMD_NAND) |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 139 | extern ulong nand_probe(ulong physadr); |
| 140 | |
| 141 | static inline void NF_Reset(void) |
| 142 | { |
| 143 | int i; |
| 144 | |
| 145 | NF_SetCE(NFCE_LOW); |
| 146 | NF_Cmd(0xFF); /* reset command */ |
| 147 | for(i = 0; i < 10; i++); /* tWB = 100ns. */ |
| 148 | NF_WaitRB(); /* wait 200~500us; */ |
| 149 | NF_SetCE(NFCE_HIGH); |
| 150 | } |
| 151 | |
| 152 | static inline void NF_Init(void) |
| 153 | { |
| 154 | #if 1 |
| 155 | #define TACLS 0 |
| 156 | #define TWRPH0 3 |
| 157 | #define TWRPH1 0 |
| 158 | #else |
| 159 | #define TACLS 0 |
| 160 | #define TWRPH0 4 |
| 161 | #define TWRPH1 2 |
| 162 | #endif |
| 163 | |
| 164 | NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); |
| 165 | /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ |
| 166 | /* 1 1 1 1, 1 xxx, r xxx, r xxx */ |
| 167 | /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ |
| 168 | |
| 169 | NF_Reset(); |
| 170 | } |
| 171 | |
| 172 | void nand_init(void) |
| 173 | { |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 174 | struct s3c2410_nand * const nand = s3c2410_get_base_nand(); |
Wolfgang Denk | 32cb2c7 | 2006-07-21 11:31:42 +0200 | [diff] [blame] | 175 | |
| 176 | NF_Init(); |
| 177 | #ifdef DEBUG |
| 178 | printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); |
| 179 | #endif |
| 180 | printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); |
| 181 | } |
Jon Loeliger | ab3abcb | 2007-07-09 18:45:16 -0500 | [diff] [blame] | 182 | #endif |
Ben Warren | b1c0eaa | 2009-08-25 13:09:37 -0700 | [diff] [blame] | 183 | |
| 184 | #ifdef CONFIG_CMD_NET |
| 185 | int board_eth_init(bd_t *bis) |
| 186 | { |
| 187 | int rc = 0; |
| 188 | #ifdef CONFIG_CS8900 |
| 189 | rc = cs8900_initialize(0, CONFIG_CS8900_BASE); |
| 190 | #endif |
| 191 | return rc; |
| 192 | } |
| 193 | #endif |