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Nobuhiro Iwamatsubd0550f2013-11-21 17:07:45 +09001/*
2 * arch/arm/include/asm/arch-rmobile/r8a7791.h
Nobuhiro Iwamatsubd0550f2013-11-21 17:07:45 +09003 *
Nobuhiro Iwamatsu5723e242014-03-27 16:11:17 +09004 * Copyright (C) 2013,2014 Renesas Electronics Corporation
Nobuhiro Iwamatsubd0550f2013-11-21 17:07:45 +09005 *
6 * SPDX-License-Identifier: GPL-2.0
Nobuhiro Iwamatsu5723e242014-03-27 16:11:17 +09007*/
Nobuhiro Iwamatsubd0550f2013-11-21 17:07:45 +09008
9#ifndef __ASM_ARCH_R8A7791_H
10#define __ASM_ARCH_R8A7791_H
11
Nobuhiro Iwamatsu5723e242014-03-27 16:11:17 +090012#include "rcar-base.h"
Nobuhiro Iwamatsubd0550f2013-11-21 17:07:45 +090013/*
Nobuhiro Iwamatsu5723e242014-03-27 16:11:17 +090014 * R-Car (R8A7791) I/O Addresses
Nobuhiro Iwamatsubd0550f2013-11-21 17:07:45 +090015 */
Nobuhiro Iwamatsua75d7f02014-11-06 16:03:47 +090016
17/* SH-I2C */
18#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
19
Nobuhiro Iwamatsu72d42ba2014-12-17 08:03:00 +090020/* SDHI */
21#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
22#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
23#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
24
Nobuhiro Iwamatsu1251e492013-11-21 17:07:46 +090025#define DBSC3_1_QOS_R0_BASE 0xE67A1000
26#define DBSC3_1_QOS_R1_BASE 0xE67A1100
27#define DBSC3_1_QOS_R2_BASE 0xE67A1200
28#define DBSC3_1_QOS_R3_BASE 0xE67A1300
29#define DBSC3_1_QOS_R4_BASE 0xE67A1400
30#define DBSC3_1_QOS_R5_BASE 0xE67A1500
31#define DBSC3_1_QOS_R6_BASE 0xE67A1600
32#define DBSC3_1_QOS_R7_BASE 0xE67A1700
33#define DBSC3_1_QOS_R8_BASE 0xE67A1800
34#define DBSC3_1_QOS_R9_BASE 0xE67A1900
35#define DBSC3_1_QOS_R10_BASE 0xE67A1A00
36#define DBSC3_1_QOS_R11_BASE 0xE67A1B00
37#define DBSC3_1_QOS_R12_BASE 0xE67A1C00
38#define DBSC3_1_QOS_R13_BASE 0xE67A1D00
39#define DBSC3_1_QOS_R14_BASE 0xE67A1E00
40#define DBSC3_1_QOS_R15_BASE 0xE67A1F00
41#define DBSC3_1_QOS_W0_BASE 0xE67A2000
42#define DBSC3_1_QOS_W1_BASE 0xE67A2100
43#define DBSC3_1_QOS_W2_BASE 0xE67A2200
44#define DBSC3_1_QOS_W3_BASE 0xE67A2300
45#define DBSC3_1_QOS_W4_BASE 0xE67A2400
46#define DBSC3_1_QOS_W5_BASE 0xE67A2500
47#define DBSC3_1_QOS_W6_BASE 0xE67A2600
48#define DBSC3_1_QOS_W7_BASE 0xE67A2700
49#define DBSC3_1_QOS_W8_BASE 0xE67A2800
50#define DBSC3_1_QOS_W9_BASE 0xE67A2900
51#define DBSC3_1_QOS_W10_BASE 0xE67A2A00
52#define DBSC3_1_QOS_W11_BASE 0xE67A2B00
53#define DBSC3_1_QOS_W12_BASE 0xE67A2C00
54#define DBSC3_1_QOS_W13_BASE 0xE67A2D00
55#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
56#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
Nobuhiro Iwamatsudbfd1152014-05-19 12:23:35 +090057#define DBSC3_1_DBADJ2 0xE67A00C8
Nobuhiro Iwamatsu1251e492013-11-21 17:07:46 +090058
Nobuhiro Iwamatsuc72dd8e2014-12-02 16:52:22 +090059/* Module stop control/status register bits */
60#define MSTP0_BITS 0x00640801
61#define MSTP1_BITS 0x9B6C9B5A
62#define MSTP2_BITS 0x100D21FC
63#define MSTP3_BITS 0xF08CD810
64#define MSTP4_BITS 0x800001C4
65#define MSTP5_BITS 0x44C00046
66#define MSTP7_BITS 0x05BFE618
67#define MSTP8_BITS 0x40C0FE85
68#define MSTP9_BITS 0xFF979FFF
69#define MSTP10_BITS 0xFFFEFFE0
70#define MSTP11_BITS 0x000001C0
71
Nobuhiro Iwamatsufb3af512014-03-28 13:43:40 +090072#define R8A7791_CUT_ES2X 2
73#define IS_R8A7791_ES2() \
74 (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
75
Nobuhiro Iwamatsubd0550f2013-11-21 17:07:45 +090076#endif /* __ASM_ARCH_R8A7791_H */