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wdenkc0218802003-03-27 12:09:35 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
wdenk5da627a2003-10-09 20:09:04 +000026#include <asm/mipsregs.h>
Shinya Kuribayashiccf8f822008-03-25 21:30:06 +090027#include <asm/cacheops.h>
Shinya Kuribayashib0c66af2008-03-25 21:30:07 +090028#include <asm/reboot.h>
Shinya Kuribayashiccf8f822008-03-25 21:30:06 +090029
30#define cache_op(op,addr) \
31 __asm__ __volatile__( \
32 " .set push \n" \
33 " .set noreorder \n" \
34 " .set mips3\n\t \n" \
35 " cache %0, %1 \n" \
36 " .set pop \n" \
37 : \
38 : "i" (op), "R" (*(unsigned char *)(addr)))
wdenkc0218802003-03-27 12:09:35 +000039
Shinya Kuribayashib0c66af2008-03-25 21:30:07 +090040void __attribute__((weak)) _machine_restart(void)
41{
42}
43
wdenkc0218802003-03-27 12:09:35 +000044int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
45{
Shinya Kuribayashib0c66af2008-03-25 21:30:07 +090046 _machine_restart();
wdenk3e386912003-04-05 00:53:31 +000047
wdenkc0218802003-03-27 12:09:35 +000048 fprintf(stderr, "*** reset failed ***\n");
49 return 0;
50}
51
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +090052void flush_cache(ulong start_addr, ulong size)
wdenkc0218802003-03-27 12:09:35 +000053{
Shinya Kuribayashiccf8f822008-03-25 21:30:06 +090054 unsigned long lsize = CFG_CACHELINE_SIZE;
55 unsigned long addr = start_addr & ~(lsize - 1);
56 unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
57
58 while (1) {
Shinya Kuribayashi188e94c2008-04-08 16:20:35 +090059 cache_op(Hit_Writeback_Inv_D, addr);
60 cache_op(Hit_Invalidate_I, addr);
Shinya Kuribayashiccf8f822008-03-25 21:30:06 +090061 if (addr == aend)
62 break;
63 addr += lsize;
64 }
wdenkc0218802003-03-27 12:09:35 +000065}
wdenk5da627a2003-10-09 20:09:04 +000066
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +090067void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
68{
wdenk5da627a2003-10-09 20:09:04 +000069 write_32bit_cp0_register(CP0_ENTRYLO0, low0);
70 write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
71 write_32bit_cp0_register(CP0_ENTRYLO1, low1);
72 write_32bit_cp0_register(CP0_ENTRYHI, hi);
73 write_32bit_cp0_register(CP0_INDEX, index);
74 tlb_write_indexed();
75}