| Stefan Roese | 537223a | 2007-08-06 21:10:17 +0200 | [diff] [blame] | 1 | The 2 important dipswitches are configured as shown below: |
| 2 | |
| 3 | SW1 (for 33MHz SysClk) |
| 4 | ---------------------- |
| 5 | S1 S2 S3 S4 S5 S6 S7 S8 |
| 6 | OFF OFF OFF OFF OFF OFF OFF ON |
| 7 | |
| 8 | SW7 (for Op-Code Flash and Boot Option H) |
| 9 | ----------------------------------------- |
| 10 | S1 S2 S3 S4 S5 S6 S7 S8 |
| 11 | OFF OFF OFF ON OFF OFF OFF OFF |
| 12 | |
| 13 | The EEPROM at location 0x52 is loaded with these 16 bytes: |
| 14 | C47042A6 05D7A190 40082350 0d050000 |
| 15 | |
| 16 | SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors |
| 17 | SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB |
| 18 | SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output |
| 19 | SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz |
| 20 | SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor |
| 21 | SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A |
| 22 | SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B |
| 23 | SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B |
| 24 | SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor |
| 25 | SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor |
| 26 | SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0 |
| 27 | SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0 |
| 28 | SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0 |
| 29 | SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer |
| 30 | SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit |
| 31 | SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC |
| 32 | SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled |
| 33 | SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled |
| 34 | SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100 |
| 35 | SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled |
| 36 | SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1 |
| 37 | SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled |
| 38 | SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC |
| 39 | SDR0_SDSTP0[NE]: 0 : NDFC: disabled |
| 40 | SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit |
| 41 | SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection |
| 42 | SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size) |
| 43 | SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled |
| 44 | SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready |
| 45 | SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter |
| 46 | SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC |
| 47 | SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC |
| 48 | SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC |
| 49 | SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC |
| 50 | SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count |
| 51 | |
| 52 | PPC440EP Clocking Configuration |
| 53 | |
| 54 | SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz |
| 55 | OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz |
| 56 | |
| 57 | The above information is reported by Eugene O'Brien |
| 58 | <Eugene.O'Brien@advantechamt.com>. Thanks a lot. |
| 59 | |
| 60 | 2007-08-06, Stefan Roese <sr@denx.de> |
| 61 | --------------------------------------------------------------------- |
| 62 | |
| Stefan Roese | 193dd95 | 2006-07-27 16:14:05 +0200 | [diff] [blame] | 63 | The configuration for the AMCC 440EP eval board "Bamboo" was changed |
| 64 | to only use 384 kbytes of FLASH for the U-Boot image. This way the |
| 65 | redundant environment can be saved in the remaining 2 sectors of the |
| 66 | same flash chip. |
| 67 | |
| 68 | Caution: With an upgrade from an earlier U-Boot version the current |
| 69 | environment will be erased since the environment is now saved in |
| 70 | different sectors. By using the following command the environment can |
| 71 | be saved after upgrading the U-Boot image and *before* resetting the |
| 72 | board: |
| 73 | |
| 74 | setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \ |
| 75 | 'cp.b FFF60000 FFF80000 20000' |
| 76 | |
| 77 | 2006-07-27, Stefan Roese <sr@denx.de> |