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Tang Yuantiana7787b72014-11-21 11:17:15 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/immap_85xx.h>
9#include "sleep.h"
Zhao Qiangae42eb02015-03-25 17:02:59 +080010#ifdef CONFIG_U_QE
11#include "../../../drivers/qe/qe.h"
12#endif
Tang Yuantiana7787b72014-11-21 11:17:15 +080013
14DECLARE_GLOBAL_DATA_PTR;
15
16void __weak board_mem_sleep_setup(void)
17{
18}
19
20void __weak board_sleep_prepare(void)
21{
22}
23
24bool is_warm_boot(void)
25{
26 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
27
28 if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
29 return 1;
30
31 return 0;
32}
33
34void fsl_dp_disable_console(void)
35{
36 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
37}
38
39/*
40 * When wakeup from deep sleep, the first 128 bytes space
41 * will be used to do DDR training which corrupts the data
42 * in there. This function will restore them.
43 */
44static void dp_ddr_restore(void)
45{
Tang Yuantian1a56fce2015-04-20 11:16:56 +080046 u64 *src, *dst;
Tang Yuantiana7787b72014-11-21 11:17:15 +080047 int i;
48 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
49
50 /* get the address of ddr date from SPARECR3 */
Tang Yuantian1a56fce2015-04-20 11:16:56 +080051 src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
52 dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
Tang Yuantiana7787b72014-11-21 11:17:15 +080053
54 for (i = 0; i < DDR_BUFF_LEN / 8; i++)
Tang Yuantian1a56fce2015-04-20 11:16:56 +080055 *dst-- = *src--;
Tang Yuantiana7787b72014-11-21 11:17:15 +080056
57 flush_dcache();
58}
59
60static void dp_resume_prepare(void)
61{
62 dp_ddr_restore();
63
64 board_sleep_prepare();
65
66 l2cache_init();
67#if defined(CONFIG_RAMBOOT_PBL)
68 disable_cpc_sram();
69#endif
70 enable_cpc();
Zhao Qiangae42eb02015-03-25 17:02:59 +080071
72#ifdef CONFIG_U_QE
73 u_qe_resume();
74#endif
75
Tang Yuantiana7787b72014-11-21 11:17:15 +080076}
77
78int fsl_dp_resume(void)
79{
80 u32 start_addr;
81 void (*kernel_resume)(void);
82 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
83
84 if (!is_warm_boot())
85 return 0;
86
87 dp_resume_prepare();
88
89 /* Get the entry address and jump to kernel */
90 start_addr = in_be32(&scfg->sparecr[1]);
91 debug("Entry address is 0x%08x\n", start_addr);
92 kernel_resume = (void (*)(void))start_addr;
93 kernel_resume();
94
95 return 0;
96}