blob: a0a3da1e82c0d00762e58ec9762e1632b7ea4e5d [file] [log] [blame]
wdenk43d96162003-03-06 00:02:04 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
4 *
5 * Configuration for the Auerswald Innokom CPU board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * include/configs/innokom.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
wdenk43d96162003-03-06 00:02:04 +000033/*
wdenk43d96162003-03-06 00:02:04 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020037#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
wdenk43d96162003-03-06 00:02:04 +000038#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
39
40#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41 /* for timer/console/ethernet */
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020042
Marek Vasutdf1ac0e2010-10-20 20:52:21 +020043#define CONFIG_SYS_TEXT_BASE 0x0
44
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020045/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000046#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020047
wdenk43d96162003-03-06 00:02:04 +000048/*
49 * Hardware drivers
50 */
51
52/*
53 * select serial console configuration
54 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020055#define CONFIG_PXA_SERIAL
wdenk43d96162003-03-06 00:02:04 +000056#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
57
58/* allow to overwrite serial and ethaddr */
59#define CONFIG_ENV_OVERWRITE
60
61#define CONFIG_BAUDRATE 19200
wdenk06d01db2003-03-14 20:47:52 +000062#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
wdenk43d96162003-03-06 00:02:04 +000063
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050064
65/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050066 * BOOTP options
67 */
68#define CONFIG_BOOTP_BOOTFILESIZE
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72
73
74/*
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050075 * Command line configuration.
76 */
77
78#define CONFIG_CMD_ASKENV
79#define CONFIG_CMD_BDI
80#define CONFIG_CMD_CACHE
81#define CONFIG_CMD_DHCP
82#define CONFIG_CMD_ECHO
Mike Frysingerbdab39d2009-01-28 19:08:14 -050083#define CONFIG_CMD_SAVEENV
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050084#define CONFIG_CMD_FLASH
85#define CONFIG_CMD_I2C
86#define CONFIG_CMD_IMI
87#define CONFIG_CMD_LOADB
88#define CONFIG_CMD_MEMORY
89#define CONFIG_CMD_NET
90#define CONFIG_CMD_RUN
91
wdenk43d96162003-03-06 00:02:04 +000092
93#define CONFIG_BOOTDELAY 3
94/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
95#define CONFIG_BOOTARGS "console=ttyS0,19200"
96#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
97#define CONFIG_NETMASK 255.255.255.0
98#define CONFIG_IPADDR 192.168.1.56
99#define CONFIG_SERVERIP 192.168.1.2
100#define CONFIG_BOOTCOMMAND "bootm 0x40000"
101#define CONFIG_SHOW_BOOT_PROGRESS
102
103#define CONFIG_CMDLINE_TAG 1
104
wdenk43d96162003-03-06 00:02:04 +0000105/*
106 * Miscellaneous configurable options
107 */
108
109/*
wdenkf6e20fc2004-02-08 19:38:38 +0000110 * Size of malloc() pool
wdenk43d96162003-03-06 00:02:04 +0000111 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_MALLOC_LEN (256*1024)
wdenk43d96162003-03-06 00:02:04 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_LONGHELP /* undef to save memory */
115#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
116#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
117#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
118#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
119#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk43d96162003-03-06 00:02:04 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
122#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenk43d96162003-03-06 00:02:04 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */
wdenk43d96162003-03-06 00:02:04 +0000125
Micha Kalfon94a33122009-02-11 19:50:11 +0200126#define CONFIG_SYS_HZ 1000
wdenk43d96162003-03-06 00:02:04 +0000127 /* RS: the oscillator is actually 3680130?? */
128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
wdenk43d96162003-03-06 00:02:04 +0000130 /* 0101000001 */
131 /* ^^^^^ Memory Speed 99.53 MHz */
132 /* ^^ Run Mode Speed = 2x Mem Speed */
133 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
wdenk43d96162003-03-06 00:02:04 +0000136
wdenk8bde7f72003-06-27 21:31:46 +0000137 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk43d96162003-03-06 00:02:04 +0000139
140/*
141 * I2C bus
142 */
Lei Wen68432c22011-04-13 23:48:16 +0530143#define CONFIG_I2C_MV 1
Lei Wen3df619e2011-04-13 23:48:31 +0530144#define CONFIG_MV_I2C_REG 0x40301680
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200145#define CONFIG_HARD_I2C 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_I2C_SPEED 50000
147#define CONFIG_SYS_I2C_SLAVE 0xfe
wdenk43d96162003-03-06 00:02:04 +0000148
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200149#define CONFIG_ENV_IS_IN_EEPROM 1
wdenk43d96162003-03-06 00:02:04 +0000150
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200151#define CONFIG_ENV_OFFSET 0x00 /* environment starts here */
152#define CONFIG_ENV_SIZE 1024 /* 1 KiB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
154#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
155#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
156#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of address */
157#define CONFIG_SYS_EEPROM_SIZE 4096 /* size in bytes */
158#define CONFIG_SYS_I2C_INIT_BOARD 1 /* board has it's own init */
wdenk06d01db2003-03-14 20:47:52 +0000159
160/*
161 * SMSC91C111 Network Card
162 */
Ben Warren7194ab82009-10-04 22:37:03 -0700163#define CONFIG_SMC91111 1
wdenk06d01db2003-03-14 20:47:52 +0000164#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
165#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
166#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
wdenkf39748a2004-06-09 13:37:52 +0000167#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */
wdenk06d01db2003-03-14 20:47:52 +0000168#undef CONFIG_SHOW_ACTIVITY
169#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
wdenk43d96162003-03-06 00:02:04 +0000170
171/*
172 * Stack sizes
173 *
174 * The stack sizes are set up in start.S using the settings below
175 */
176#define CONFIG_STACKSIZE (128*1024) /* regular stack */
177#ifdef CONFIG_USE_IRQ
178#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
179#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
180#endif
181
182/*
183 * Physical Memory Map
184 */
185#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
186#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
187#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
188
189#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
190#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */
193#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenk43d96162003-03-06 00:02:04 +0000194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenk43d96162003-03-06 00:02:04 +0000196
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200197#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200198#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200199
wdenk06d01db2003-03-14 20:47:52 +0000200/*
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200201 * JFFS2 partitions
202 *
wdenk06d01db2003-03-14 20:47:52 +0000203 */
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200204/* development flash */
205#define CONFIG_MTD_INNOKOM_16MB 1
206#undef CONFIG_MTD_INNOKOM_64MB
wdenk06d01db2003-03-14 20:47:52 +0000207
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200208/* production flash */
209/*
210#define CONFIG_MTD_INNOKOM_64MB 1
211#undef CONFIG_MTD_INNOKOM_16MB
212*/
213
214/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100215#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200216#define CONFIG_JFFS2_DEV "nor0"
217#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
218#define CONFIG_JFFS2_PART_OFFSET 0x00000000
219
220/* mtdparts command line support */
221/* Note: fake mtd_id used, no linux mtd map file */
222/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100223#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200224#define MTDIDS_DEFAULT "nor0=innokom-0"
225*/
226
227/* development flash */
228/*
229#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
230*/
231
232/* production flash */
233/*
234#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
235*/
wdenk06d01db2003-03-14 20:47:52 +0000236
237/*
wdenk3e386912003-04-05 00:53:31 +0000238 * GPIO settings
wdenk06d01db2003-03-14 20:47:52 +0000239 *
240 * GP15 == nCS1 is 1
wdenk43d96162003-03-06 00:02:04 +0000241 * GP24 == SFRM is 1
242 * GP25 == TXD is 1
243 * GP33 == nCS5 is 1
244 * GP39 == FFTXD is 1
245 * GP41 == RTS is 1
246 * GP47 == TXD is 1
247 * GP49 == nPWE is 1
248 * GP62 == LED_B is 1
249 * GP63 == TDM_OE is 1
250 * GP78 == nCS2 is 1
251 * GP79 == nCS3 is 1
252 * GP80 == nCS4 is 1
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_GPSR0_VAL 0x03008000
255#define CONFIG_SYS_GPSR1_VAL 0xC0028282
256#define CONFIG_SYS_GPSR2_VAL 0x0001C000
wdenk43d96162003-03-06 00:02:04 +0000257
258/* GP02 == DON_RST is 0
259 * GP23 == SCLK is 0
260 * GP45 == USB_ACT is 0
261 * GP60 == PLLEN is 0
262 * GP61 == LED_A is 0
263 * GP73 == SWUPD_LED is 0
264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_GPCR0_VAL 0x00800004
266#define CONFIG_SYS_GPCR1_VAL 0x30002000
267#define CONFIG_SYS_GPCR2_VAL 0x00000100
wdenk43d96162003-03-06 00:02:04 +0000268
269/* GP00 == DON_READY is input
270 * GP01 == DON_OK is input
271 * GP02 == DON_RST is output
272 * GP03 == RESET_IND is input
273 * GP07 == RES11 is input
274 * GP09 == RES12 is input
275 * GP11 == SWUPDATE is input
276 * GP14 == nPOWEROK is input
277 * GP15 == nCS1 is output
278 * GP17 == RES22 is input
279 * GP18 == RDY is input
280 * GP23 == SCLK is output
281 * GP24 == SFRM is output
282 * GP25 == TXD is output
283 * GP26 == RXD is input
284 * GP32 == RES21 is input
285 * GP33 == nCS5 is output
286 * GP34 == FFRXD is input
287 * GP35 == CTS is input
288 * GP39 == FFTXD is output
289 * GP41 == RTS is output
290 * GP42 == USB_OK is input
291 * GP45 == USB_ACT is output
292 * GP46 == RXD is input
293 * GP47 == TXD is output
294 * GP49 == nPWE is output
295 * GP58 == nCPUBUSINT is input
296 * GP59 == LANINT is input
297 * GP60 == PLLEN is output
298 * GP61 == LED_A is output
299 * GP62 == LED_B is output
300 * GP63 == TDM_OE is output
301 * GP64 == nDSPINT is input
302 * GP65 == STRAP0 is input
303 * GP67 == STRAP1 is input
304 * GP69 == STRAP2 is input
305 * GP70 == STRAP3 is input
306 * GP71 == STRAP4 is input
307 * GP73 == SWUPD_LED is output
308 * GP78 == nCS2 is output
309 * GP79 == nCS3 is output
310 * GP80 == nCS4 is output
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_GPDR0_VAL 0x03808004
313#define CONFIG_SYS_GPDR1_VAL 0xF002A282
314#define CONFIG_SYS_GPDR2_VAL 0x0001C200
wdenk43d96162003-03-06 00:02:04 +0000315
316/* GP15 == nCS1 is AF10
317 * GP18 == RDY is AF01
318 * GP23 == SCLK is AF10
319 * GP24 == SFRM is AF10
320 * GP25 == TXD is AF10
321 * GP26 == RXD is AF01
322 * GP33 == nCS5 is AF10
323 * GP34 == FFRXD is AF01
324 * GP35 == CTS is AF01
325 * GP39 == FFTXD is AF10
326 * GP41 == RTS is AF10
327 * GP46 == RXD is AF10
328 * GP47 == TXD is AF01
329 * GP49 == nPWE is AF10
330 * GP78 == nCS2 is AF10
331 * GP79 == nCS3 is AF10
332 * GP80 == nCS4 is AF10
333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
335#define CONFIG_SYS_GAFR0_U_VAL 0x001A8010
336#define CONFIG_SYS_GAFR1_L_VAL 0x60088058
337#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
338#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
339#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenk43d96162003-03-06 00:02:04 +0000340
wdenk06d01db2003-03-14 20:47:52 +0000341
wdenk43d96162003-03-06 00:02:04 +0000342/* FIXME: set GPIO_RER/FER */
343
344/* RDH = 1
345 * PH = 1
346 * VFS = 1
347 * BFS = 1
348 * SSS = 1
349 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_PSSR_VAL 0x37
wdenk43d96162003-03-06 00:02:04 +0000351
Marek Vasutdf1ac0e2010-10-20 20:52:21 +0200352#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
353#define CONFIG_SYS_CKEN 0x0
354
wdenk43d96162003-03-06 00:02:04 +0000355/*
356 * Memory settings
wdenk06d01db2003-03-14 20:47:52 +0000357 *
358 * This is the configuration for nCS0/1 -> flash banks
wdenk43d96162003-03-06 00:02:04 +0000359 * configuration for nCS1:
360 * [31] 0 - Slower Device
361 * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
362 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
363 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
364 * [19] 1 - 16 Bit bus width
365 * [18:16] 000 - nonburst RAM or FLASH
366 * configuration for nCS0:
367 * [15] 0 - Slower Device
368 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
369 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
370 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
371 * [03] 1 - 16 Bit bus width
372 * [02:00] 000 - nonburst RAM or FLASH
373 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */
wdenk43d96162003-03-06 00:02:04 +0000375
376/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
377 * configuration for nCS3: DSP
378 * [31] 0 - Slower Device
379 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
380 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
381 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
382 * [19] 1 - 16 Bit bus width
383 * [18:16] 100 - variable latency I/O
384 * configuration for nCS2: TDM-Switch
385 * [15] 0 - Slower Device
386 * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
387 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
388 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
389 * [03] 1 - 16 Bit bus width
390 * [02:00] 100 - variable latency I/O
391 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */
wdenk43d96162003-03-06 00:02:04 +0000393
394/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
395 *
396 * configuration for nCS5: LAN Controller
397 * [31] 0 - Slower Device
398 * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
399 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
400 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
401 * [19] 1 - 16 Bit bus width
402 * [18:16] 100 - variable latency I/O
403 * configuration for nCS4: ExtBus
404 * [15] 0 - Slower Device
405 * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
406 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
407 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
408 * [03] 1 - 16 Bit bus width
409 * [02:00] 100 - variable latency I/O
410 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
wdenk43d96162003-03-06 00:02:04 +0000412
413/* MDCNFG: SDRAM Configuration Register
414 *
415 * [31:29] 000 - reserved
416 * [28] 0 - no SA1111 compatiblity mode
417 * [27] 0 - latch return data with return clock
418 * [26] 0 - alternate addressing for pair 2/3
419 * [25:24] 00 - timings
420 * [23] 0 - internal banks in lower partition 2/3 (not used)
421 * [22:21] 00 - row address bits for partition 2/3 (not used)
422 * [20:19] 00 - column address bits for partition 2/3 (not used)
423 * [18] 0 - SDRAM partition 2/3 width is 32 bit
424 * [17] 0 - SDRAM partition 3 disabled
425 * [16] 0 - SDRAM partition 2 disabled
426 * [15:13] 000 - reserved
427 * [12] 1 - SA1111 compatiblity mode
428 * [11] 1 - latch return data with return clock
429 * [10] 0 - no alternate addressing for pair 0/1
wdenk06d01db2003-03-14 20:47:52 +0000430 * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
wdenk43d96162003-03-06 00:02:04 +0000431 * [7] 1 - 4 internal banks in lower partition pair
432 * [06:05] 10 - 13 row address bits for partition 0/1
433 * [04:03] 01 - 9 column address bits for partition 0/1
434 * [02] 0 - SDRAM partition 0/1 width is 32 bit
435 * [01] 0 - disable SDRAM partition 1
436 * [00] 1 - enable SDRAM partition 0
wdenk43d96162003-03-06 00:02:04 +0000437 */
wdenk06d01db2003-03-14 20:47:52 +0000438/* use the configuration above but disable partition 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_MDCNFG_VAL 0x000019c8
wdenk43d96162003-03-06 00:02:04 +0000440
441/* MDREFR: SDRAM Refresh Control Register
442 *
443 * [32:26] 0 - reserved
444 * [25] 0 - K2FREE: not free running
445 * [24] 0 - K1FREE: not free running
wdenk3e386912003-04-05 00:53:31 +0000446 * [23] 1 - K0FREE: not free running
wdenk43d96162003-03-06 00:02:04 +0000447 * [22] 0 - SLFRSH: self refresh disabled
448 * [21] 0 - reserved
449 * [20] 0 - APD: no auto power down
450 * [19] 0 - K2DB2: SDCLK2 is MemClk
451 * [18] 0 - K2RUN: disable SDCLK2
452 * [17] 0 - K1DB2: SDCLK1 is MemClk
453 * [16] 1 - K1RUN: enable SDCLK1
454 * [15] 1 - E1PIN: SDRAM clock enable
455 * [14] 1 - K0DB2: SDCLK0 is MemClk
wdenk3e386912003-04-05 00:53:31 +0000456 * [13] 0 - K0RUN: disable SDCLK0
wdenk43d96162003-03-06 00:02:04 +0000457 * [12] 1 - E0PIN: disable SDCKE0
458 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
459 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_MDREFR_VAL 0x0081D018
wdenk43d96162003-03-06 00:02:04 +0000461
462/* MDMRS: Mode Register Set Configuration Register
463 *
464 * [31] 0 - reserved
465 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
466 * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
467 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
468 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
469 * [15] 0 - reserved
470 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
471 * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
472 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
473 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
474 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_MDMRS_VAL 0x00020022
wdenk43d96162003-03-06 00:02:04 +0000476
477/*
478 * PCMCIA and CF Interfaces
479 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_MECR_VAL 0x00000000
481#define CONFIG_SYS_MCMEM0_VAL 0x00000000
482#define CONFIG_SYS_MCMEM1_VAL 0x00000000
483#define CONFIG_SYS_MCATT0_VAL 0x00000000
484#define CONFIG_SYS_MCATT1_VAL 0x00000000
485#define CONFIG_SYS_MCIO0_VAL 0x00000000
486#define CONFIG_SYS_MCIO1_VAL 0x00000000
wdenk43d96162003-03-06 00:02:04 +0000487
Marek Vasutdf1ac0e2010-10-20 20:52:21 +0200488#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
489#define CONFIG_SYS_SXCNFG_VAL 0x00000000
490
wdenk43d96162003-03-06 00:02:04 +0000491/*
492#define CSB226_USER_LED0 0x00000008
493#define CSB226_USER_LED1 0x00000010
494#define CSB226_USER_LED2 0x00000020
495*/
496
497/*
498 * FLASH and environment organization
499 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
501#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
wdenk43d96162003-03-06 00:02:04 +0000502
503/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
505#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk43d96162003-03-06 00:02:04 +0000506
wdenk43d96162003-03-06 00:02:04 +0000507#endif /* __CONFIG_H */