blob: 03aedeca53eea1e06b5de1b061c1965ad2214220 [file] [log] [blame]
Dave Liu19580e62007-09-18 12:37:57 +08001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef __CONFIG_H
22#define __CONFIG_H
23
Dave Liu19580e62007-09-18 12:37:57 +080024/*
25 * High Level Configuration Options
26 */
27#define CONFIG_E300 1 /* E300 family */
Peter Tyser0f898602009-05-22 17:23:24 -050028#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050029#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
Dave Liu19580e62007-09-18 12:37:57 +080030#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
31
Wolfgang Denk2ae18242010-10-06 09:05:45 +020032#define CONFIG_SYS_TEXT_BASE 0xFE000000
33
Dave Liu19580e62007-09-18 12:37:57 +080034/*
35 * System Clock Setup
36 */
37#ifdef CONFIG_PCISLAVE
38#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
39#else
40#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
41#endif
42
43#ifndef CONFIG_SYS_CLK_FREQ
44#define CONFIG_SYS_CLK_FREQ 66000000
45#endif
46
47/*
48 * Hardware Reset Configuration Word
49 * if CLKIN is 66MHz, then
50 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
51 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_HRCW_LOW (\
Dave Liu19580e62007-09-18 12:37:57 +080053 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
54 HRCWL_DDR_TO_SCB_CLK_1X1 |\
55 HRCWL_SVCOD_DIV_2 |\
56 HRCWL_CSB_TO_CLKIN_6X1 |\
57 HRCWL_CORE_TO_CSB_1_5X1)
58
59#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080061 HRCWH_PCI_AGENT |\
62 HRCWH_PCI1_ARBITER_DISABLE |\
63 HRCWH_CORE_ENABLE |\
64 HRCWH_FROM_0XFFF00100 |\
65 HRCWH_BOOTSEQ_DISABLE |\
66 HRCWH_SW_WATCHDOG_DISABLE |\
67 HRCWH_ROM_LOC_LOCAL_16BIT |\
68 HRCWH_RL_EXT_LEGACY |\
69 HRCWH_TSEC1M_IN_RGMII |\
70 HRCWH_TSEC2M_IN_RGMII |\
71 HRCWH_BIG_ENDIAN |\
72 HRCWH_LDP_CLEAR)
73#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080075 HRCWH_PCI_HOST |\
76 HRCWH_PCI1_ARBITER_ENABLE |\
77 HRCWH_CORE_ENABLE |\
78 HRCWH_FROM_0X00000100 |\
79 HRCWH_BOOTSEQ_DISABLE |\
80 HRCWH_SW_WATCHDOG_DISABLE |\
81 HRCWH_ROM_LOC_LOCAL_16BIT |\
82 HRCWH_RL_EXT_LEGACY |\
83 HRCWH_TSEC1M_IN_RGMII |\
84 HRCWH_TSEC2M_IN_RGMII |\
85 HRCWH_BIG_ENDIAN |\
86 HRCWH_LDP_CLEAR)
87#endif
88
Dave Liubd4458c2008-03-04 16:59:22 +080089/* Arbiter Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
91#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
Dave Liubd4458c2008-03-04 16:59:22 +080092
93/* System Priority Control Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
Dave Liubd4458c2008-03-04 16:59:22 +080095
Dave Liu19580e62007-09-18 12:37:57 +080096/*
Dave Liubd4458c2008-03-04 16:59:22 +080097 * IP blocks clock configuration
Dave Liu19580e62007-09-18 12:37:57 +080098 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
100#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
101#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
Dave Liu19580e62007-09-18 12:37:57 +0800102
103/*
104 * System IO Config
105 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_SICRH 0x00000000
107#define CONFIG_SYS_SICRL 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +0800108
109/*
110 * Output Buffer Impedance
111 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_OBIR 0x31100000
Dave Liu19580e62007-09-18 12:37:57 +0800113
114#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
115#define CONFIG_BOARD_EARLY_INIT_R
Anton Vorontsovc78c6782009-06-10 00:25:31 +0400116#define CONFIG_HWCONFIG
Dave Liu19580e62007-09-18 12:37:57 +0800117
118/*
119 * IMMR new address
120 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu19580e62007-09-18 12:37:57 +0800122
123/*
124 * DDR Setup
125 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
127#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
128#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
129#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
130#define CONFIG_SYS_83XX_DDR_USES_CS0
131#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */
Dave Liu19580e62007-09-18 12:37:57 +0800132
133#undef CONFIG_DDR_ECC /* support DDR ECC function */
134#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
135
136#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
137#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
138
139#if defined(CONFIG_SPD_EEPROM)
140#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
141#else
142/*
143 * Manually set up DDR parameters
Dave Liu7e74d632008-01-10 23:07:23 +0800144 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
Dave Liu19580e62007-09-18 12:37:57 +0800145 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_DDR_SIZE 512 /* MB */
148#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
149#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
Dave Liu19580e62007-09-18 12:37:57 +0800150 | 0x00010000 /* ODT_WR to CSn */ \
151 | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
152 /* 0x80010202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_DDR_TIMING_3 0x00000000
154#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
Dave Liu19580e62007-09-18 12:37:57 +0800155 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
156 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
157 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
158 | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
159 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
160 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
161 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
162 /* 0x00620802 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
Dave Liu19580e62007-09-18 12:37:57 +0800164 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
165 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
166 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
167 | (13 << TIMING_CFG1_REFREC_SHIFT ) \
168 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
169 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
170 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
171 /* 0x3935d322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
Dave Liu19580e62007-09-18 12:37:57 +0800173 | ( 6 << TIMING_CFG2_CPO_SHIFT ) \
174 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
175 | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
176 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
177 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
178 | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
Dave Liu7e74d632008-01-10 23:07:23 +0800179 /* 0x131088c8 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
Dave Liu19580e62007-09-18 12:37:57 +0800181 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
182 /* 0x03E00100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
184#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
185#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
Dave Liu19580e62007-09-18 12:37:57 +0800186 | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
Dave Liu7e74d632008-01-10 23:07:23 +0800187 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +0800189#endif
190
191/*
192 * Memory test
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
195#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
196#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liu19580e62007-09-18 12:37:57 +0800197
198/*
199 * The reserved memory
200 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200201#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dave Liu19580e62007-09-18 12:37:57 +0800202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
204#define CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800205#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#undef CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800207#endif
208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400210#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liu19580e62007-09-18 12:37:57 +0800212
213/*
214 * Initial RAM Base Address Setup
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_INIT_RAM_LOCK 1
217#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200218#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200219#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu19580e62007-09-18 12:37:57 +0800220
221/*
222 * Local Bus Configuration & Clock Setup
223 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500224#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
225#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_LBC_LBCR 0x00000000
Becky Bruce0914f482010-06-17 11:37:18 -0500227#define CONFIG_FSL_ELBC 1
Dave Liu19580e62007-09-18 12:37:57 +0800228
229/*
230 * FLASH on the Local Bus
231 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200233#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
235#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
236#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu19580e62007-09-18 12:37:57 +0800237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
239#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
Dave Liu19580e62007-09-18 12:37:57 +0800240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
Dave Liuded08312008-01-10 23:08:26 +0800242 | (2 << BR_PS_SHIFT) /* 16 bit port size */ \
243 | BR_V ) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
Dave Liuded08312008-01-10 23:08:26 +0800245 | OR_UPM_XAM \
246 | OR_GPCM_CSNT \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400247 | OR_GPCM_ACS_DIV2 \
Dave Liuded08312008-01-10 23:08:26 +0800248 | OR_GPCM_XACS \
249 | OR_GPCM_SCY_15 \
250 | OR_GPCM_TRLX \
251 | OR_GPCM_EHTR \
252 | OR_GPCM_EAD )
253 /* 0xFE000FF7 */
Dave Liu19580e62007-09-18 12:37:57 +0800254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
256#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Dave Liu19580e62007-09-18 12:37:57 +0800257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#undef CONFIG_SYS_FLASH_CHECKSUM
259#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
260#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liu19580e62007-09-18 12:37:57 +0800261
262/*
263 * BCSR on the Local Bus
264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_BCSR 0xF8000000
266#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
267#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
Dave Liu19580e62007-09-18 12:37:57 +0800268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
270#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
Dave Liu19580e62007-09-18 12:37:57 +0800271
272/*
273 * NAND Flash on the Local Bus
274 */
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400275#define CONFIG_CMD_NAND 1
276#define CONFIG_MTD_NAND_VERIFY_WRITE 1
277#define CONFIG_SYS_MAX_NAND_DEVICE 1
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400278#define CONFIG_NAND_FSL_ELBC 1
279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
281#define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \
Dave Liu19580e62007-09-18 12:37:57 +0800282 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
283 | BR_PS_8 /* Port Size = 8 bit */ \
284 | BR_MS_FCM /* MSEL = FCM */ \
285 | BR_V ) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400287 | OR_FCM_BCTLD \
Dave Liu19580e62007-09-18 12:37:57 +0800288 | OR_FCM_CST \
289 | OR_FCM_CHT \
290 | OR_FCM_SCY_1 \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400291 | OR_FCM_RST \
Dave Liu19580e62007-09-18 12:37:57 +0800292 | OR_FCM_TRLX \
293 | OR_FCM_EHTR )
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400294 /* 0xFFFF919E */
Dave Liu19580e62007-09-18 12:37:57 +0800295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
297#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
Dave Liu19580e62007-09-18 12:37:57 +0800298
299/*
300 * Serial Port
301 */
302#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_NS16550
304#define CONFIG_SYS_NS16550_SERIAL
305#define CONFIG_SYS_NS16550_REG_SIZE 1
306#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu19580e62007-09-18 12:37:57 +0800307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_BAUDRATE_TABLE \
Dave Liu19580e62007-09-18 12:37:57 +0800309 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
312#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu19580e62007-09-18 12:37:57 +0800313
314/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_HUSH_PARSER
316#ifdef CONFIG_SYS_HUSH_PARSER
317#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Dave Liu19580e62007-09-18 12:37:57 +0800318#endif
319
320/* Pass open firmware flat tree */
321#define CONFIG_OF_LIBFDT 1
322#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600323#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Dave Liu19580e62007-09-18 12:37:57 +0800324
325/* I2C */
326#define CONFIG_HARD_I2C /* I2C with hardware support */
327#undef CONFIG_SOFT_I2C /* I2C bit-banged */
328#define CONFIG_FSL_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
330#define CONFIG_SYS_I2C_SLAVE 0x7F
331#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
332#define CONFIG_SYS_I2C_OFFSET 0x3000
333#define CONFIG_SYS_I2C2_OFFSET 0x3100
Dave Liu19580e62007-09-18 12:37:57 +0800334
335/*
336 * Config on-board RTC
337 */
338#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu19580e62007-09-18 12:37:57 +0800340
341/*
342 * General PCI
343 * Addresses are mapped 1-1.
344 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
346#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
347#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
348#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
349#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
350#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
351#define CONFIG_SYS_PCI_IO_BASE 0x00000000
352#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
353#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu19580e62007-09-18 12:37:57 +0800354
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
356#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
357#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu19580e62007-09-18 12:37:57 +0800358
Anton Vorontsov8b345572009-01-08 04:26:19 +0300359#define CONFIG_SYS_PCIE1_BASE 0xA0000000
360#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
361#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
362#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
363#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
364#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
365#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
366#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
367#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
368
369#define CONFIG_SYS_PCIE2_BASE 0xC0000000
370#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
371#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
372#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
373#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
374#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
375#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
376#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
377#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
378
Dave Liu19580e62007-09-18 12:37:57 +0800379#ifdef CONFIG_PCI
Anton Vorontsov00f7bba2008-10-02 19:17:33 +0400380#ifndef __ASSEMBLY__
381extern int board_pci_host_broken(void);
382#endif
Kim Phillipsbe9b56d2009-07-23 14:09:38 -0500383#define CONFIG_PCIE
Dave Liu19580e62007-09-18 12:37:57 +0800384#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
385
Anton Vorontsov3bf1be32008-10-14 22:58:53 +0400386#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
387
Dave Liu19580e62007-09-18 12:37:57 +0800388#define CONFIG_PCI_PNP /* do pci plug-and-play */
389
390#undef CONFIG_EEPRO100
391#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu19580e62007-09-18 12:37:57 +0800393#endif /* CONFIG_PCI */
394
Dave Liu19580e62007-09-18 12:37:57 +0800395/*
396 * TSEC
397 */
398#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_TSEC1_OFFSET 0x24000
400#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
401#define CONFIG_SYS_TSEC2_OFFSET 0x25000
402#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liu19580e62007-09-18 12:37:57 +0800403
404/*
405 * TSEC ethernet configuration
406 */
407#define CONFIG_MII 1 /* MII PHY management */
408#define CONFIG_TSEC1 1
409#define CONFIG_TSEC1_NAME "eTSEC0"
410#define CONFIG_TSEC2 1
411#define CONFIG_TSEC2_NAME "eTSEC1"
412#define TSEC1_PHY_ADDR 2
413#define TSEC2_PHY_ADDR 3
Anton Vorontsov1da83a62008-10-02 18:32:25 +0400414#define TSEC1_PHY_ADDR_SGMII 8
415#define TSEC2_PHY_ADDR_SGMII 4
Dave Liu19580e62007-09-18 12:37:57 +0800416#define TSEC1_PHYIDX 0
417#define TSEC2_PHYIDX 0
418#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
419#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
420
421/* Options are: TSEC[0-1] */
422#define CONFIG_ETHPRIME "eTSEC1"
423
Dave Liu6f8c85e2008-03-26 22:56:36 +0800424/* SERDES */
425#define CONFIG_FSL_SERDES
426#define CONFIG_FSL_SERDES1 0xe3000
427#define CONFIG_FSL_SERDES2 0xe3100
428
Dave Liu19580e62007-09-18 12:37:57 +0800429/*
Dave Liu2eeb3e42008-03-26 22:57:19 +0800430 * SATA
431 */
432#define CONFIG_LIBATA
433#define CONFIG_FSL_SATA
434
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_SATA_MAX_DEVICE 2
Dave Liu2eeb3e42008-03-26 22:57:19 +0800436#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_SATA1_OFFSET 0x18000
438#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
439#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800440#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_SATA2_OFFSET 0x19000
442#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
443#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800444
445#ifdef CONFIG_FSL_SATA
446#define CONFIG_LBA48
447#define CONFIG_CMD_SATA
448#define CONFIG_DOS_PARTITION
449#define CONFIG_CMD_EXT2
450#endif
451
452/*
Dave Liu19580e62007-09-18 12:37:57 +0800453 * Environment
454 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200456 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200458 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
459 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800460#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200462 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200464 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800465#endif
466
467#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu19580e62007-09-18 12:37:57 +0800469
470/*
471 * BOOTP options
472 */
473#define CONFIG_BOOTP_BOOTFILESIZE
474#define CONFIG_BOOTP_BOOTPATH
475#define CONFIG_BOOTP_GATEWAY
476#define CONFIG_BOOTP_HOSTNAME
477
478
479/*
480 * Command line configuration.
481 */
482#include <config_cmd_default.h>
483
484#define CONFIG_CMD_PING
485#define CONFIG_CMD_I2C
486#define CONFIG_CMD_MII
487#define CONFIG_CMD_DATE
488
489#if defined(CONFIG_PCI)
490 #define CONFIG_CMD_PCI
491#endif
492
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500494 #undef CONFIG_CMD_SAVEENV
Dave Liu19580e62007-09-18 12:37:57 +0800495 #undef CONFIG_CMD_LOADS
496#endif
497
498#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500499#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu19580e62007-09-18 12:37:57 +0800500
501#undef CONFIG_WATCHDOG /* watchdog disabled */
502
Andy Fleminge1ac3872008-10-30 16:50:14 -0500503#define CONFIG_MMC 1
504
505#ifdef CONFIG_MMC
506#define CONFIG_FSL_ESDHC
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800507#define CONFIG_FSL_ESDHC_PIN_MUX
Andy Fleminge1ac3872008-10-30 16:50:14 -0500508#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
509#define CONFIG_CMD_MMC
510#define CONFIG_GENERIC_MMC
511#define CONFIG_CMD_EXT2
512#define CONFIG_CMD_FAT
513#define CONFIG_DOS_PARTITION
514#endif
515
Dave Liu19580e62007-09-18 12:37:57 +0800516/*
517 * Miscellaneous configurable options
518 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519#define CONFIG_SYS_LONGHELP /* undef to save memory */
520#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
521#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Dave Liu19580e62007-09-18 12:37:57 +0800522
523#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800525#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200526 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800527#endif
528
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200529#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
530#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
531#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
532#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Dave Liu19580e62007-09-18 12:37:57 +0800533
534/*
535 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700536 * have to be in the first 256 MB of memory, since this is
Dave Liu19580e62007-09-18 12:37:57 +0800537 * the maximum mapped by the Linux kernel during initialization.
538 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700539#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Dave Liu19580e62007-09-18 12:37:57 +0800540
541/*
542 * Core HID Setup
543 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500544#define CONFIG_SYS_HID0_INIT 0x000000000
545#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
546 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu19580e62007-09-18 12:37:57 +0800548
549/*
Dave Liu19580e62007-09-18 12:37:57 +0800550 * MMU Setup
551 */
Becky Bruce31d82672008-05-08 19:02:12 -0500552#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liu19580e62007-09-18 12:37:57 +0800553
554/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200555#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
556#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Dave Liu19580e62007-09-18 12:37:57 +0800557
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200558#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
559#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
560#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
561#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu19580e62007-09-18 12:37:57 +0800562
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
564#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
565#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
566#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu19580e62007-09-18 12:37:57 +0800567
568/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200569#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \
Dave Liu19580e62007-09-18 12:37:57 +0800570 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200571#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
572#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
573#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu19580e62007-09-18 12:37:57 +0800574
575/* BCSR: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200576#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_10 | \
Dave Liu19580e62007-09-18 12:37:57 +0800577 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200578#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
579#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
580#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu19580e62007-09-18 12:37:57 +0800581
582/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200583#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
584#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
585#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
Dave Liu19580e62007-09-18 12:37:57 +0800586 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200587#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu19580e62007-09-18 12:37:57 +0800588
589/* Stack in dcache: cacheable, no memory coherence */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200590#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
591#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
592#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
593#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu19580e62007-09-18 12:37:57 +0800594
595#ifdef CONFIG_PCI
596/* PCI MEM space: cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200597#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
598#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
599#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
600#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu19580e62007-09-18 12:37:57 +0800601/* PCI MMIO space: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
Dave Liu19580e62007-09-18 12:37:57 +0800603 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200604#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
605#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
606#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800607#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200608#define CONFIG_SYS_IBAT6L (0)
609#define CONFIG_SYS_IBAT6U (0)
610#define CONFIG_SYS_IBAT7L (0)
611#define CONFIG_SYS_IBAT7U (0)
612#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
613#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
614#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
615#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800616#endif
617
Dave Liu19580e62007-09-18 12:37:57 +0800618#if defined(CONFIG_CMD_KGDB)
619#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
620#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
621#endif
622
623/*
624 * Environment Configuration
625 */
626
627#define CONFIG_ENV_OVERWRITE
628
629#if defined(CONFIG_TSEC_ENET)
630#define CONFIG_HAS_ETH0
Dave Liu19580e62007-09-18 12:37:57 +0800631#define CONFIG_HAS_ETH1
Dave Liu19580e62007-09-18 12:37:57 +0800632#endif
633
634#define CONFIG_BAUDRATE 115200
635
Kim Phillips79f516b2009-08-21 16:34:38 -0500636#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu19580e62007-09-18 12:37:57 +0800637
638#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
639#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
640
641#define CONFIG_EXTRA_ENV_SETTINGS \
642 "netdev=eth0\0" \
643 "consoledev=ttyS0\0" \
644 "ramdiskaddr=1000000\0" \
645 "ramdiskfile=ramfs.83xx\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500646 "fdtaddr=780000\0" \
Kim Phillips270fe262008-03-07 12:27:31 -0600647 "fdtfile=mpc8379_mds.dtb\0" \
Dave Liu19580e62007-09-18 12:37:57 +0800648 ""
649
650#define CONFIG_NFSBOOTCOMMAND \
651 "setenv bootargs root=/dev/nfs rw " \
652 "nfsroot=$serverip:$rootpath " \
653 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
654 "console=$consoledev,$baudrate $othbootargs;" \
655 "tftp $loadaddr $bootfile;" \
656 "tftp $fdtaddr $fdtfile;" \
657 "bootm $loadaddr - $fdtaddr"
658
659#define CONFIG_RAMBOOTCOMMAND \
660 "setenv bootargs root=/dev/ram rw " \
661 "console=$consoledev,$baudrate $othbootargs;" \
662 "tftp $ramdiskaddr $ramdiskfile;" \
663 "tftp $loadaddr $bootfile;" \
664 "tftp $fdtaddr $fdtfile;" \
665 "bootm $loadaddr $ramdiskaddr $fdtaddr"
666
667
668#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
669
670#endif /* __CONFIG_H */