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wdenk03f5c552004-10-10 21:21:55 +00001/*
2 * Copyright 2004 Freescale Semiconductor.
3 *
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenk03f5c552004-10-10 21:21:55 +000025#include <common.h>
26#include <pci.h>
27#include <asm/processor.h>
Jon Loeligeraa11d852008-03-17 15:48:18 -050028#include <asm/mmu.h>
wdenk03f5c552004-10-10 21:21:55 +000029#include <asm/immap_85xx.h>
Jon Loeligeraa11d852008-03-17 15:48:18 -050030#include <asm/fsl_ddr_sdram.h>
Wolfgang Denk2d5df632005-07-21 16:14:36 +020031#include <ioports.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060032#include <spd_sdram.h>
Kumar Galab90d2542007-11-29 00:11:44 -060033#include <libfdt.h>
34#include <fdt_support.h>
wdenk03f5c552004-10-10 21:21:55 +000035
36#include "../common/cadmus.h"
37#include "../common/eeprom.h"
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -050038#include "../common/via.h"
wdenk03f5c552004-10-10 21:21:55 +000039
Jon Loeligerd9b94f22005-07-25 14:05:07 -050040#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk03f5c552004-10-10 21:21:55 +000041extern void ddr_enable_ecc(unsigned int dram_size);
42#endif
43
wdenk03f5c552004-10-10 21:21:55 +000044void local_bus_init(void);
45void sdram_init(void);
46
Wolfgang Denk2d5df632005-07-21 16:14:36 +020047/*
48 * I/O Port configuration table
49 *
50 * if conf is 1, then that port pin will be configured at boot time
51 * according to the five values podr/pdir/ppar/psor/pdat for that entry
52 */
53
54const iop_conf_t iop_conf_tab[4][32] = {
55
56 /* Port A configuration */
57 { /* conf ppar psor pdir podr pdat */
58 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
59 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
60 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
61 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
62 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
63 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
64 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
65 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
66 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
67 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
68 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
69 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
70 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
71 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
72 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
73 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
74 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
75 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
76 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
77 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
78 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
79 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
80 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
81 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
82 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
83 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
84 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
85 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
86 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
87 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
88 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
89 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
90 },
91
92 /* Port B configuration */
93 { /* conf ppar psor pdir podr pdat */
94 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
95 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
96 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
97 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
98 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
99 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
100 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
101 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
102 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
103 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
104 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
105 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
106 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
107 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
108 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
109 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
110 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
111 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
112 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
113 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
114 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
116 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
117 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
118 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
120 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
121 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
122 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
123 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
124 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
125 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
126 },
127
128 /* Port C */
129 { /* conf ppar psor pdir podr pdat */
130 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
131 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
132 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
133 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
134 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
135 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
136 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
137 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
138 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
139 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
140 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
141 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
142 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
143 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
144 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
145 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
146 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
147 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
148 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
149 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
150 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
151 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
152 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
153 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
154 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
155 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
156 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
157 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
158 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
159 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
160 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
161 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
162 },
163
164 /* Port D */
165 { /* conf ppar psor pdir podr pdat */
166 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
167 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
168 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
169 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
170 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
171 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
172 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
173 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
174 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
175 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
176 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
177 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
178 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
179 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
180 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
181 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
182 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
183 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
184 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
185 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
186 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
187 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
188 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
189 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
190 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
191 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
192 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
193 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
194 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
195 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
196 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
197 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
198 }
199};
200
wdenk5c952cf2004-10-10 21:27:30 +0000201int checkboard (void)
wdenk03f5c552004-10-10 21:21:55 +0000202{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
wdenk03f5c552004-10-10 21:21:55 +0000204
wdenk5c952cf2004-10-10 21:27:30 +0000205 /* PCI slot in USER bits CSR[6:7] by convention. */
206 uint pci_slot = get_pci_slot ();
wdenk03f5c552004-10-10 21:21:55 +0000207
wdenk5c952cf2004-10-10 21:27:30 +0000208 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
209 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
210 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
211 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
wdenk03f5c552004-10-10 21:21:55 +0000212
wdenk5c952cf2004-10-10 21:27:30 +0000213 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
wdenk03f5c552004-10-10 21:21:55 +0000214
wdenk5c952cf2004-10-10 21:27:30 +0000215 uint cpu_board_rev = get_cpu_board_revision ();
wdenk03f5c552004-10-10 21:21:55 +0000216
wdenk5c952cf2004-10-10 21:27:30 +0000217 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
218 get_board_version (), pci_slot);
wdenk03f5c552004-10-10 21:21:55 +0000219
wdenk5c952cf2004-10-10 21:27:30 +0000220 printf ("CPU Board Revision %d.%d (0x%04x)\n",
221 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
222 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
wdenk03f5c552004-10-10 21:21:55 +0000223
wdenk5c952cf2004-10-10 21:27:30 +0000224 printf (" PCI1: %d bit, %s MHz, %s\n",
225 (pci1_32) ? 32 : 64,
226 (pci1_speed == 33000000) ? "33" :
227 (pci1_speed == 66000000) ? "66" : "unknown",
228 pci1_clk_sel ? "sync" : "async");
wdenk03f5c552004-10-10 21:21:55 +0000229
wdenk5c952cf2004-10-10 21:27:30 +0000230 if (pci_dual) {
231 printf (" PCI2: 32 bit, 66 MHz, %s\n",
232 pci2_clk_sel ? "sync" : "async");
233 } else {
234 printf (" PCI2: disabled\n");
235 }
wdenk03f5c552004-10-10 21:21:55 +0000236
wdenk5c952cf2004-10-10 21:27:30 +0000237 /*
238 * Initialize local bus.
239 */
240 local_bus_init ();
wdenk03f5c552004-10-10 21:21:55 +0000241
wdenk5c952cf2004-10-10 21:27:30 +0000242 return 0;
wdenk03f5c552004-10-10 21:21:55 +0000243}
244
Becky Bruce9973e3c2008-06-09 16:03:40 -0500245phys_size_t
wdenk03f5c552004-10-10 21:21:55 +0000246initdram(int board_type)
247{
248 long dram_size = 0;
wdenk03f5c552004-10-10 21:21:55 +0000249
250 puts("Initializing\n");
251
252#if defined(CONFIG_DDR_DLL)
253 {
254 /*
255 * Work around to stabilize DDR DLL MSYNC_IN.
256 * Errata DDR9 seems to have been fixed.
257 * This is now the workaround for Errata DDR11:
258 * Override DLL = 1, Course Adj = 1, Tap Select = 0
259 */
260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
wdenk03f5c552004-10-10 21:21:55 +0000262
263 gur->ddrdllcr = 0x81000000;
264 asm("sync;isync;msync");
265 udelay(200);
266 }
267#endif
Jon Loeligeraa11d852008-03-17 15:48:18 -0500268 dram_size = fsl_ddr_sdram();
269 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
270 dram_size *= 0x100000;
wdenk03f5c552004-10-10 21:21:55 +0000271
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500272#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk03f5c552004-10-10 21:21:55 +0000273 /*
274 * Initialize and enable DDR ECC.
275 */
276 ddr_enable_ecc(dram_size);
277#endif
wdenk03f5c552004-10-10 21:21:55 +0000278 /*
279 * SDRAM Initialization
280 */
281 sdram_init();
282
283 puts(" DDR: ");
284 return dram_size;
285}
286
wdenk03f5c552004-10-10 21:21:55 +0000287/*
288 * Initialize Local Bus
289 */
wdenk03f5c552004-10-10 21:21:55 +0000290void
291local_bus_init(void)
292{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
294 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
wdenk03f5c552004-10-10 21:21:55 +0000295
296 uint clkdiv;
297 uint lbc_hz;
298 sys_info_t sysinfo;
299 uint temp_lbcdll;
300
301 /*
302 * Errata LBC11.
303 * Fix Local Bus clock glitch when DLL is enabled.
304 *
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200305 * If localbus freq is < 66MHz, DLL bypass mode must be used.
306 * If localbus freq is > 133MHz, DLL can be safely enabled.
wdenk03f5c552004-10-10 21:21:55 +0000307 * Between 66 and 133, the DLL is enabled with an override workaround.
308 */
309
310 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800311 clkdiv = lbc->lcrr & LCRR_CLKDIV;
wdenk03f5c552004-10-10 21:21:55 +0000312 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
313
314 if (lbc_hz < 66) {
315 lbc->lcrr |= 0x80000000; /* DLL Bypass */
316
317 } else if (lbc_hz >= 133) {
318 lbc->lcrr &= (~0x80000000); /* DLL Enabled */
319
320 } else {
321 lbc->lcrr &= (~0x8000000); /* DLL Enabled */
322 udelay(200);
323
324 /*
325 * Sample LBC DLL ctrl reg, upshift it to set the
326 * override bits.
327 */
328 temp_lbcdll = gur->lbcdllcr;
329 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
330 asm("sync;isync;msync");
331 }
332}
333
wdenk03f5c552004-10-10 21:21:55 +0000334/*
335 * Initialize SDRAM memory on the Local Bus.
336 */
wdenk03f5c552004-10-10 21:21:55 +0000337void
338sdram_init(void)
339{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
wdenk03f5c552004-10-10 21:21:55 +0000341
342 uint idx;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
344 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
wdenk03f5c552004-10-10 21:21:55 +0000345 uint cpu_board_rev;
346 uint lsdmr_common;
347
348 puts(" SDRAM: ");
349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
wdenk03f5c552004-10-10 21:21:55 +0000351
352 /*
353 * Setup SDRAM Base and Option Registers
354 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355 lbc->or2 = CONFIG_SYS_OR2_PRELIM;
wdenk03f5c552004-10-10 21:21:55 +0000356 asm("msync");
357
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358 lbc->br2 = CONFIG_SYS_BR2_PRELIM;
wdenk03f5c552004-10-10 21:21:55 +0000359 asm("msync");
360
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
wdenk03f5c552004-10-10 21:21:55 +0000362 asm("msync");
363
364
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
366 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
wdenk03f5c552004-10-10 21:21:55 +0000367 asm("msync");
368
369 /*
370 * Determine which address lines to use baed on CPU board rev.
371 */
372 cpu_board_rev = get_cpu_board_revision();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
wdenk03f5c552004-10-10 21:21:55 +0000374 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375 lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
wdenk03f5c552004-10-10 21:21:55 +0000376 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377 lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
wdenk03f5c552004-10-10 21:21:55 +0000378 } else {
379 /*
380 * Assume something unable to identify itself is
381 * really old, and likely has lines 16/17 mapped.
382 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383 lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
wdenk03f5c552004-10-10 21:21:55 +0000384 }
385
386 /*
387 * Issue PRECHARGE ALL command.
388 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
wdenk03f5c552004-10-10 21:21:55 +0000390 asm("sync;msync");
391 *sdram_addr = 0xff;
392 ppcDcbf((unsigned long) sdram_addr);
393 udelay(100);
394
395 /*
396 * Issue 8 AUTO REFRESH commands.
397 */
398 for (idx = 0; idx < 8; idx++) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
wdenk03f5c552004-10-10 21:21:55 +0000400 asm("sync;msync");
401 *sdram_addr = 0xff;
402 ppcDcbf((unsigned long) sdram_addr);
403 udelay(100);
404 }
405
406 /*
407 * Issue 8 MODE-set command.
408 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
wdenk03f5c552004-10-10 21:21:55 +0000410 asm("sync;msync");
411 *sdram_addr = 0xff;
412 ppcDcbf((unsigned long) sdram_addr);
413 udelay(100);
414
415 /*
416 * Issue NORMAL OP command.
417 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
wdenk03f5c552004-10-10 21:21:55 +0000419 asm("sync;msync");
420 *sdram_addr = 0xff;
421 ppcDcbf((unsigned long) sdram_addr);
422 udelay(200); /* Overkill. Must wait > 200 bus cycles */
423
424#endif /* enable SDRAM init */
425}
426
wdenk03f5c552004-10-10 21:21:55 +0000427#if defined(CONFIG_PCI)
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500428/* For some reason the Tundra PCI bridge shows up on itself as a
429 * different device. Work around that by refusing to configure it.
wdenk03f5c552004-10-10 21:21:55 +0000430 */
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500431void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
wdenk03f5c552004-10-10 21:21:55 +0000432
wdenk03f5c552004-10-10 21:21:55 +0000433static struct pci_config_table pci_mpc85xxcds_config_table[] = {
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500434 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700435 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
436 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
Andy Flemingffa621a2007-02-24 01:08:13 -0600437 mpc85xx_config_via_usbide, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700438 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
439 mpc85xx_config_via_usb, {0,0,0}},
440 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
441 mpc85xx_config_via_usb2, {0,0,0}},
442 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
Andy Flemingffa621a2007-02-24 01:08:13 -0600443 mpc85xx_config_via_power, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700444 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
445 mpc85xx_config_via_ac97, {0,0,0}},
Andy Flemingffa621a2007-02-24 01:08:13 -0600446 {},
wdenk03f5c552004-10-10 21:21:55 +0000447};
wdenk03f5c552004-10-10 21:21:55 +0000448
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500449static struct pci_controller hose[] = {
450 { config_table: pci_mpc85xxcds_config_table,},
451#ifdef CONFIG_MPC85XX_PCI2
452 {},
wdenk03f5c552004-10-10 21:21:55 +0000453#endif
454};
455
456#endif /* CONFIG_PCI */
457
wdenk03f5c552004-10-10 21:21:55 +0000458void
459pci_init_board(void)
460{
461#ifdef CONFIG_PCI
Matthew McClintock7376eb82006-10-11 15:13:01 -0500462 pci_mpc85xx_init(hose);
wdenk03f5c552004-10-10 21:21:55 +0000463#endif
464}
Kumar Galab90d2542007-11-29 00:11:44 -0600465
466#if defined(CONFIG_OF_BOARD_SETUP)
467void
468ft_pci_setup(void *blob, bd_t *bd)
469{
470 int node, tmp[2];
471 const char *path;
472
473 node = fdt_path_offset(blob, "/aliases");
474 tmp[0] = 0;
475 if (node >= 0) {
476#ifdef CONFIG_PCI1
477 path = fdt_getprop(blob, node, "pci0", NULL);
478 if (path) {
479 tmp[1] = hose[0].last_busno - hose[0].first_busno;
480 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
481 }
482#endif
483#ifdef CONFIG_MPC85XX_PCI2
484 path = fdt_getprop(blob, node, "pci1", NULL);
485 if (path) {
486 tmp[1] = hose[1].last_busno - hose[1].first_busno;
487 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
488 }
489#endif
490 }
491}
492#endif